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Patrick Yin
Chiang |
|
| Department
of Electrical & Computer Engineering |
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| Oregon State
University |
| Corvallis, OR
97331-3211 |
| Phone: (541)
737-5551 |
| Fax: (541) 737-1300
|
| Email:
pchiang@eecs.oregonstate.edu
|
|
Web
Page |
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| Education |
|
Ph.D. (EE), Stanford University, 2006 |
| M.S.
(EE), Stanford University, 2001 |
|
B.S. (EECS), University of California-Berkeley, 1987 |
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| Research
Areas & Special Interests |
| Design and implementation of new architectures for
mixed-signal circuits (high-speed serial links, RF circuit design) in
deep submicron CMOS; low power, high data rate, parallel I/Os; 20+GHz,
4-5 bit low power ADC; reconfigurable, self-healing RF transceiver
with digital on-die calibration |
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| Recent
CDADIC Projects
(see
"Research" page for projects) |
|
Comparisons
and Tradeoffs Between Mixed-Signal Equalizers and a High-Speed Low
Resolution ADC for High-Speed Serial Links, 2006-2007 |
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