Description of Projects Funded
2002-2003

Low Power Wireless Sensor for Space and Military Applications

SOI-CMOS Temp-Rad 
R. Bruce Darling (University of Washington) with Fong Shi (Boeing)

Direct Digital Frequency Synthesizer for Reconfigurable Communication Systems
George La Rue and Valeriu Beiui (Washington State University ) with Fong Shi (Boeing)

SOI CMOS Continuos-Time Delta-Sigma A/D Converters for Space Communication Radio Receivers 
Adrian Leuciuc (State University of New York at Stony Brook ) with Bruce Ohme (Honeywell)

Radiation Hard PLL Design Tolerant to Noise and Process Variation
Un-Ku Moon and Karti Mayaram (Oregon State University ) with Paul Bauhahn (Honeywell)

RF, Analog and Digital Array for Radiation-Hardened Communication Circuits
Carl Sechen and Larry McMurchie (University of Washington ) with Andy Peczalski (Honeywell)

Design of Radiation-Hard Analog/Mixed Signal Circuits in Silicon-on-Insulator Technology
S. Subramanian and Gabor Temes (Oregon State University) with Andy Peczalski (Honeywell)

CDADIC Funded Projects, 2002-2003

Calibration Techniques for Low-Voltage CMOS Folding/Interpolating A/D Converters

Principal Investigator:  David Allstot and Ward Helms (University of Washington)
Participating Students:  Waisiu Law and and Jianjun Guo

This research project is a continuation of previous CDADIC work developing circuit techniques and calibration/correction algorithms for low-voltage, one-bit per stage pipelined A/D converters implemented in fine-line CMOS technology. The goal is to develop 10 bits at 100Ms/s. The project also will investigate a novel range shifting technique for INL correction of a 1.5-bit per stage pipeline converter design. Progress thus far includes: the completion of a behavioral simulation study on the effects of non-ideal amplifiers and comparators in determining the correction factors for pipelined ADCs; development of a new calibration approach for a one-bit per stage pipeline ADC to eliminate potential non-monotonicity due to nonlinear amplifiers; and completed proof of concept simulations on a 1.5-bit per stage ADC using a novel voltage shifting method, which avoids driving the amplifiers output into their nonlinear ranges, hence greatly improving INL.

This research is unique in that the improved technique is able to remove all non-monotonic output codes due to non-ideal components in a manner that is more efficient than some existing approaches. The new method for calibrating a 1.5-bit per stage ADC avoids the highly non-linear regions of the amplifier outputs by applying an input-dependent level-shifting scheme. CDADIC-member companies will benefit by using these new methods. They can design ADC circuits using less demanding amplifier and comparator specifications resulting from smaller geometries and the lower-power supply voltages associated with technology scaling. The system noise performance is improved because a large signal range is maintained even at low supply voltages.

Compact Modeling of ESD Protection Systems for CMOS-3

Principal Investigator:  R. Bruce Darling (University of Washington)
Participating Students:  Yeshwant Subramanian

Compact models for ESD protection systems are being developed so that circuit simulators can be used to predict and assess ESD protection system effectiveness for a complete CMOS IC. The objective of this work is to elevate ESD modeling and simulation from the device level to the full chip level, which will support an overall structured, hierarchical design of custom ESD protection systems and pad frames, in parallel to what is presently done for the core of an IC. This research will develop improved device models for avalanche breakdown diodes, zener diodes, and bipolar transistor structures by adding improved characteristics for reverse breakdown and high forward currents. Dynamically coupled electrothermal effects will be added to model energy flow during an ESD event. Improved layout extraction for pad rings will be developed to parameterize the parasitic elements that become important for ESD events. These models are being validated against ESD pulse measurements on pad frame test devices.

This research is novel in that it emphasizes compact modeling in which the device physics is reduced to a closely coupled set of ordinary differential equations that can be integrated into a circuit simulation model. ESD protection involves close interactions between the protection devices and their embedded circuit, so this approach is necessary to fully evaluate any ESD scheme. CDADIC-member companies will benefit from this research by allowing modeling and simulation of IC pad frame structures that could lead to improved pad frame designs and early detection of ESD protection system problems. Pad frame protection structures are usually complex and no compact models presently exist for them.

High-Frequency VCO-Based Delta-Sigma ADC in SiGe

Principal Investigator:  Terri Fiez (Oregon State University)
Participating Students:  To-be-determined

The focus of this work is to develop a new ADC that uses a VCO to create a multi-bit quantizer in a delta-sigma modulator. The target specs are 10 bits at 1GHz in a SiGe Process. The performance bottleneck of most mixed-signal systems is the A/D converter. As process dimensions reduce to realize the cost-performance benefits predicted by Moore’s Law, it becomes more difficult to obtain both high-speed and high-resolution A/D converters required in many modern communication systems. The focus of this project is to develop a new ADC architecture and demonstrate its performance by implementing it in a SiGe technology. In this area, other researchers have worked on multi-bit, delta-sigma architectures, but this research is the first based on a VCO approach.

The architecture outlined in this CDADIC project is unique because it uses a VCO to generate multiple levels in time rather than in space. CDADIC-member companies will gain from this unique architecture, which could open up a new way to develop very high-speed and high-resolution converters. It is anticipated that other novel circuit techniques also will be developed in this work that can be used in other applications as well.

FUNDING: $40,000

Clock and Data Recovery Circuits

Principal Investigator:  George La Rue (Washington State University)
Participating Students: Xiaoming Li and Ruiyuan Zhang

This project will investigate clock and data recovery (CDR) circuit design techniques in SiGe BiCMOS technology. The CDR circuits will be designed for ½-rate clocks with operation near 1 Gbps for the CMOS versions and near 40 Gbps for the SiGe HBT versions. Researchers will design both a conventional analog phase-lock loop (PLL), which has low clock jitter but a fairly long acquisition time, and a novel method that has much faster acquisition and has comparably low-clock jitter. The novel CDR circuit consists of a phase selector, which can lock to the data in just a few clock cycles but has high jitter, combined with a PLL, which requires a much longer lock time but provides a low-jitter clock after it does lock. Methods to reduce the acquisition time of the PLL in the novel CDR will be investigated. This project will provide a more complete set of interconnect models based on extensive characterization of test structures. This project is unique because it explores a novel CDR concept that combines the best features, fast acquisition and low jitter, of digital phase selection and PLL CDR circuits. Usually designers are required to pick either fast acquisition or low jitter. Combining a demux and a CDR with an on-chip VCO has not yet been done at 40 Gbps. Reducing the PLL acquisition time using the phase selection information is also novel.

CDADIC-member companies will benefit from this work, because it will demonstrate a CDR circuit that has a wider range of applications than conventional CDR circuits. For networks with fast switching between nodes, the short acquisition time reduces the number of preamble bits and results in higher efficiency. The lower clock jitter after PLL acquisition compared with other fast acquisition CDR circuits will result in lower BER after the PLL acquires lock. This CDR circuit can also be used for applications where short acquisition time is not important since its clock jitter will be comparable with PLL-only CDR circuits. This research will develop models and cells in a process that will be available to all member companies through MOSIS. Member companies will have access to interconnect and device models in IBM’s 0.5-micron BiCMOS/SiGe process, available through MOSIS. They also will have a digital standard cell library and have some characterized analog circuits as a starting point for their particular mixed-signal designs.

High-Speed A/D Converters in Low-Voltage Standard CMOS Processes

Principal Investigator: Adrian Leuciuc (State University of New York, Stony Brook)
Participating Students: Ovidui Carnu and Yi Zhang

This research effort focuses on the development of low-voltage, high-speed data converters implemented in standard and mixed-signal CMOS processes. As one of the bottlenecks of low-voltage mixed-mode IC design is represented by the availability of true low-voltage analog circuitry, this research proposes new circuit design techniques to override the limitations of deep sub-micron CMOS technology that are encountered in the design of analog cells. The project has two major tasks: implementation of a continuous-time delta-sigma modulator for next generation wireless devices, and the design of a low-latency high-speed A/D converter using folding and interpolation techniques.

This project will build upon last year’s research. During this phase, researchers will complete the layout for the 1.8V delta-sigma modulator, and fabricate and characterize a first prototype. A set of top-level design automation tools for continuous-time delta-sigma modulators will be developed and an efficiency analysis of folding and interpolating A/D converters will be conducted in order to obtain optimal architectures for a given speed and resolution. In addition, a systematic design procedure for the input folding stage with active resistive averaging is being developed and a new current-steering folding block is being analyzed with higher operation speed and reduced power consumption.

From this research, CDADIC members will gain a design methodology for current-mode continuous-time delta-sigma modulators; topologies for low-noise, linear transconductors in low-voltage CMOS standard processes; and averaging techniques for high-speed (flash and folding) A/D converters enabling the increase of their resolution and bandwidth.

FUNDING: $50,000

Communications System Specification and Simulation for Wireless Sensors

Principal Investigator:  Huaping Liu (Oregon State University)
Participating Students:  Sudheer Vemulapalli and Yu Zhang

Researches will perform system simulations to develop circuit block specifications for a low-power wireless sensor system. The objectives are to reduce cable mass and increase thermal isolation in commercial and space applications. Specific target applications include commercial aircraft landing gear and other sensors where wiring represents a difficult protection problem with high weight and cost. The project also targets spacecraft sensors to decrease launch costs associated with cable mass and to provide satellite constellations a communications interface. The next generation space telescope is a target application to eliminate the thermal barrier

penetration represented by wiring between the telescope and signal processing and control electronics. The wireless sensor radio developed in the project will operate in the 2.20 to 2.29 GHz frequency band. The radio will be a novel low-power direct conversion transceiver, frequency division duplex for at least six parallel channels. The system is designed to be a communications hub that services an array of existing ultra low power sensors (previously developed under by DARPA).

CDADIC companies will benefit from this research if they are involved in design of analog, mixed-signal circuits, ICs and communication systems. They will be able to use the research outcomes to specify requirements of new circuits, understand tradeoffs, and optimize a system’s architecture. The critical elements of a wireless network will be specified in this project and designed by an associated CDADIC project. This project will demonstrate feasibility, develop performance specifications, and provide a user flexible simulation system to develop application wireless sensor networks.

FUNDING: $40,000 

RF Power Amplifier Design Using Non-Linear Feedback Linearization

Principal Investigators:  Mario Magana (Oregon State University) and David Allstot (University of Washington)
Participating Students:  To-be-determined

This project uses, for the first time, "disturbance observer" control techniques to linearize inherently non-linear radio frequency (RF) power amplifiers. Both linear and non-linear feedback implementations are considered for applications in mobile communications such as CDMA2000 and W-CDMA, and in wireless LAN such as 802.11a. By complementing the up-conversion function in the transmitter forward path with down-conversion mixing in the feedback control path, baseband linearity correction is realized. This assures low-power linearity correction with high stability and tolerance to process, voltage, and temperature variations. Implementations are planned in fine-line CMOS and SiGe CMOS technologies. During the initial phases of this project, both linear and non-linear versions of the disturbance observer control techniques will be studied to linearize inherently non-linear CMOS RF power

amplifiers that have already been developed by the co-PI of this project. After the analysis phase, an extensive high-level simulation study using MATLAB will be undertaken, followed by circuit design and simulation using SPECTRE. Finally, researchers will employ both simulated annealing and particle swarm optimization techniques to perform parasitic and package aware optimization using layout extraction information. Chip fabrication and testing will complete the program.

Potential member company benefits include research, development, and demonstration of new RF PA linearization methods; and early use of intellectual property, patents, etc. related to project development.

FUNDING: $45,000

Low-Voltage Analog Circuits in CMOS Technology

Principal Investigator:  Un-Ku Moon (Oregon State University)
Participating Students:  Dong-Young Chang, Charlie Yun, Jipeng Li, Ki-Seok Yoo, and David Bruneau

This research investigates circuit techniques suitable for use in low-voltage sub-micron CMOS technology. Implementation solutions are targeted in the area of switched-capacitor circuits, high-accuracy data converters, and filters. Researchers will design low-voltage .S modulators and pipelined A/D converter that use the opamp-reset (OR) technique. They will also explore other methods where switched-capacitors circuits that do not require clock-voltage boosting in low-voltage operation. There are multiple prototype ICs already sent for fabrication. Full characterization will be done by the end of this summer. The recent prototype ICs sent for fabrication include, 1-V bandpass .S modulator and 1-V 15-bit calibrated algorithmic ADC. Continuing work includes the design of calibrated high resolution pipelined ADC and low-voltage linear continuous-time filters.

The novel low-voltage switched-capacitor techniques developed in this research can overcome the inherent speed limitations of the switched-opamp technique, while keeping with transistor and voltage down scaling in CMOS processes. Member companies will benefit from this work by gaining newly developed low-voltage circuits (without clock-voltage boosters) that overcome inherent switched-opamp limitations, and hence are useful for higher speed applications that may be fabricated in future state-of-the-art low-voltage CMOS technology.

FUNDING: $55,000

Noise and Performance Optimization of RF SOI CMOS Voltage Controlled Oscillators

Principal Investigator: Mohamed Osman (Washington State University)
Participating Students:  Arash Daghighi and Mawahib Sulieman

This project will continue the investigation of techniques to optimize the noise characteristics and performance of RF VCOs fabricated using Silicon-on-Insulator (SOI). Past funding has allowed the design and submission for fabrication of 2.4 GHz bulk CMOS VCO using AMI 0.35mm process, and design, simulation, and layout of 2.4GHz, 5.0 GHz, and 10.0 GHz SOI VCO’s. Simulations have demonstrated that 0.35 SOI based VCO’s exhibit: better phase noise, larger tuning range, and lower power consumption compared to bulk MOSFET. During this phase II, the bulk and SOI VCOs will be tested and characterized and new BT SOI MOSFETs and test structures for extracting the SOI sub-circuit model parameters will be fabricated and characterized. The body tied-to-source (BTS or BT) PD SOI MOSFETs exhibit better noise performance than floating body PD MOSFETs. However, the active device area is larger than FB devices with same current drive due to the area allocated to body contacts. Therefore, researchers in this project will investigate new area efficient BT SOI MOSFETs that enhance the current drive and switching characteristics in small geometry devices.

Understanding the merits of SOI technology for RF applications and how it compares with bulk CMOS will benefit CDADIC members. The performance of active and passive components in both technologies in RF range will be demonstrated.

FUNDING: $40,000 

PLL Design, Clock Generation and High-Speed/Low-Power DSP-Block Design

Principal Investigator:  Carl Sechen and Larry McMurchie (University of Washington)
Participating Students:  Samuel Kio, Sheng Sun, Alfred Chong, Jinyao Zhang, Sunny Guo, Robert Hance, Miodrag Vujkovic and Takashi Takahashi

This project is centered on two, highly-related major themes. The first concerns PLL design, DLL design and clock generation. The second theme is the design of high-speed and low-power DSP blocks. One of the logic techniques that will be used to design the very high-speed DSP blocks is output prediction logic (OPL), developed under previous CDADIC grants. OPL requires the generation and distribution of high precision, low-skew clocks in order to obtain unprecedented speed. Researchers will fabricate and test a digitally controlled 200MHz to 4GHz DLL-based clock generator. The clock frequency can be switched within a reference clock cycle. In addition, it can be turned on and off to any desired frequency without needing to reacquire locking. This approach will generate much higher clock frequencies than the best previous DLL-based approach. Project engineers also will fabricate and test a new self-adjusting frequency multiplier-based clock generator that uses neither a PLL nor DLL. In addition, they will fabricate a PLL, a new DLL-based clock generator, and a new self-adjusting frequency multiplier-based clock generator on the same chip, so that they face similar process variations, similar noise, and have the same input clock signal. Then they will be compared for jitter and other attributes. Lowest power and highest speed DSP blocks will be designed and employed both low power and high speed static CMOS design techniques as well as OPL techniques.

The project’s highly applicable lower jitter, high-frequency clock generation techniques will benefit CDADIC industry members, as well as having access to the highest speed and lowest power DSP block architectures, designs and synthesis flows.

FUNDING: $55,000 

High-Performance Delta-Sigma Converters

Principal Investigator: Gabor Temes (Oregon State University)
Participating Students: Mingliang Liu, János Markus, José Silva, and Xuesheng Wang

This research deals with on-line digital correction techniques for compensating the effects of analog circuit imperfections in high-performance, delta-sigma data converters. The first-generation MASH ADC prototype, with 13-bit 12-MS/s target specifications, was found to have a fundamental problem that these researchers are now troubleshooting. A second-generation MASH ADC (16-bit 25-MS/s) also is being designed. The first stage uses a reduced distortion architecture, a 5-bit ADC, and a 5-bit DAC with fully-digital correction. The second stage (a 10-bit ADC followed by a digital adaptive filter) operates at half the clock speed. The proposed plan is (1) to design, fabricate and test the second-generation prototype; (2) to continue the research on mixed-mode and fully digital methods for linearizing multibit DACs, and (3) to eventually combine the developed techniques in a third-generation ADC.

The principles and architectures developed under this project allow for delta-sigma conversion that does not rely on analog circuit accuracy, and can therefore be used even for future submicron technologies. High-speed and long-term high-performance operation is assured by a combination of different innovations, such as low-distortion wideband topologies, adaptive compensation of analog imperfections, and analog or fully-digital correction methods for DAC nonlinearities. Fast (5-25 MS/s) and high-resolution (13-16 bits) ADCs are needed in such applications as high-definition video and xDSL. The converters and design methodologies developed under this project should be beneficial to companies active in these and related areas.

FUNDING: $55,000

On-Chip Interconnect Models for High-Frequency/Speed-Integrated Circuits on Silicon Substrate

Principal Investigator:  Andreas Weisshaar and Vijai Tripathi (Oregon State University)
Participating Students: Amy Luoh, Hai Lan, and Dan Melendy

The overall objective of this project is the development of efficient CAD-oriented models for on-chip interconnects and spiral inductors for modern silicon-based RF, high-speed analog, and mixed-signal ICs. Physics-based, closed-form expressions for the frequency-dependent series resistance and inductance parameters are developed to accurately represent the skin and proximity effects in the on-chip metalization for interconnects and spiral inductors. Ideal-element equivalent circuits are developed and extracted from the frequency-dependent series resistance and inductance parameters to obtain causal and passive models for broadband time-and frequency-domain simulations. The new complex image approach for efficient modeling of substrate eddy-current loss is extended to multi-layer lossy substrates. The models are validated by comparison with rigorous EM simulation and measurement data.

Project researchers will develop closed-form expressions to capture the conductor skin and proximity effects in on-chip interconnects and spiral inductors using a physics-based approach. Compact ideal-element equivalent circuit models that incorporate skin and proximity effects will then be developed and extracted for short and longer interconnects. Test structures will be designed to validate the models by comparison with measurement results. The complex image approach for efficient modeling of eddy-current loss in the silicon substrate will be extended to multi-layer lossy substrates. The models for skin and proximity effect and the extended image approach for multi-layer lossy substrates will be incorporated into an interconnect modeling tool and scalable spiral inductor models, designed by project researchers. Member companies will benefit from this work by obtaining compact models for skin and proximity effect in on-chip interconnects, an interconnect modeling tool, and enhanced scalable spiral inductor models.

FUNDING: $55,000

AFRL Funded Projects, 2002-2003

 

Low Power Wireless Sensor for Space and Military Applications

University-Industry Team: David Allstot and Ward Helms (University of Washington) and Huaping Liu (Oregon State University) with Gary Nelson and Steve Fahley (Boeing)

The primary objectives of this project are to reduce cable mass and increase thermal isolation in a variety of future space and military applications similar to the Space Station, Next Generation Space Telescope, PowerSail, and satellite constellations. Other goals include reduced cost, increased reconfigurability, increased flexibility for threat reporting systems, and increased inter-satellite communications for satellite constellations. The RadHard Radio developed in this project will operate in the 2.20-2.29GHz frequency band. Emphasis is on novel low-power direct-conversion transceiver circuits, including radiation hardened design and layout methods in a fully-depleted SOI process.

Building on Boeing’s experience in developing a remote sensor for wireless applications, these researchers will develop a low-power, direct-conversion RadHard Radio operating in the 2.20-2.29GHz frequency band. The use of a direct conversion transceiver architecture enables maximum reconfigurability through the use of a mixed-signal/DSP baseband processor, which is an integral part of this effort. Circuit and layout techniques will be used to facilitate the design of a true RadHard Radio. The first three months of the program involve system definition, simulation, and circuit specification. The final nine months include circuit design, parasitic-and package-aware optimization, SOI circuit layout, and development of reconfigurable DSP algorithms.

SOI-CMOS Temp-Rad Device Models for Space Applications

University-Industry Team: R. Bruce Darling (University of Washington) with Fong Shi (Boeing)

The rapid development of advanced electronic systems for space is now requiring faster turn, more complex integrated systems to be developed that rely increasingly upon circuit simulation. However, there do not exist any SPICE MOSFET models that accurately predict device behavior over the wider temperature range and radiation exposure of space. This project will develop predictive SPICE MOSFET models that include the effects of more extreme temperatures and the effects of ionizing radiation. These models will be modified versions of the industry standard Berkeley BSIM3 model that has been recently extended to the BSIMSOI model for partially-depleted silicon-on-insulator (SOI) process technologies. Thermal modeling will be based upon the known device physics of temperature-dependent carrier transport and energy band alignments. An improved carrier mobility model will be implemented to treat a wider temperature range, as well as modifications to the energy bandgap, Fermi levels, carrier lifetimes, and effective masses. Radiation effects will be introduced by the addition of ionization current sources in each pn-junction and channel depletion region that will allow the MOSFET model to predict the effects of steady state and transient ionizing radiation. Existing test data will be used to validate the temperature dependences, and the radiation effects will be validated by experimental measurements of device response to optically induced electron-hole-pair generation. The resulting validated SPICE MOSFET models will provide a circuit and system level simulation tool to be used for VLSI circuit implementations and will provide predictive radiation effects modeling to be carried out on these designs. These models will find immediate use in the simulation of other projects that involve the design of specific circuit modules.

Direct Digital Frequency Synthesizer for Reconfigurable

Communication Systems

University-Industry Team: George La Rue and Valeriu Beiu (Washington State University) with Fong Shi (Boeing)

This project will investigate the implementation of direct digital frequency synthesizers (DDFSs) in silicon-on-insulator (SOI) CMOS technology for space applications. DDFSs provide very fast frequency hopping, low-phase noise, and high-frequency resolution, which are important requirements for many modern wireless communication systems. DDFSs are more versatile than VCO-based synthesizers and are reconfigurable after deployment to meet a wide variety of applications. This is important for space applications where the life of a mission can be very long, requirements may change, and replacing electronics after deployment is usually not an option.

Two approaches for the implementation of DDFSs will be investigated. The first approach uses a standard binary DAC and investigates algorithms that minimize both power dissipation and the amount of ROM look-up table required. The second approach uses a non-linear DAC, which requires a much smaller lookup table. Honeywell’s radiation-tolerant MOI 5 0.35 mm SOI CMOS process will be used to implement the DDFSs. The DAC resolution will be 12 bits and will use a current steering architecture for a sampling frequency near 2 GSps.

SOI CMOS Continuous-Time Delta-Sigma A/D Converters for Space Communication Radio Receivers

University-Industry Team: Adrian Leuciuc (State University of New York at Stony Brook) with Bruce Ohme (Honeywell)

This project focuses on the design of A/D converters to be used in radio receivers for space communications. Delta-sigma oversampling A/D converters realize an optimum trade-off between circuit complexity, cost, and power dissipation, high accuracy being achieved with low precision analog components. Continuous-time implementations of delta-sigma modulators have already proven to offer the advantages of lower power consumption and higher frequency operation compared to switched-capacitor counterparts. It is also envisaged, based on the fact that CT realizations do not fold high frequency perturbations back into the band, that radiation effects (especially single events transients) will not affect their performance. Combined with the advantages of SOI CMOS technology, the researchers expect to obtain extremely low-power, wide bandwidth, radiation immune A/D converters. Researchers in this project will design and evaluate two topologies for delta-sigma modulators: a band-pass configuration to be used in a heterodyne RF receiver and an A/D conversion at the IF level. The second configuration is a low-pass approach for direct down-conversion receivers and/or baseband applications.

Radiation Hard PLL Design Tolerant to Noise and Process Variation

University-Industry Team: Un-Ku Moon and Karti Mayaram (Oregon State University) with Paul Bauhahn (Honeywell)

This project addresses the design of radiation hard and noise tolerant phase-locked loops (PLLs) for frequencies greater than 1GHz in the Honeywell 0.35m m SOI CMOS (MOI-5) process. The overall focus is on a systematic design methodology for radiation-hard, noise tolerant PLLs in SOI CMOS processes. New circuits and architectures will be developed and combined with self-calibration methods. The self-calibration methods will enable tuning out process, temperature, threshold voltage, and supply voltage variations yielding a robust design. Floating-body devices will be compared with body-tied devices in the context of the PLL design and their effect on the PLL jitter/phase noise performance will also be evaluated.

The project focus is on two of the key building blocks of a PLL. These are the charge-pump based loop filter and the voltage controlled oscillator (VCO). The SOI specific issues that will be addressed here are the floating body, kink effect, and self heating. Both LC and ring type of VCO architectures will be implemented for a fully integrated solution of the PLL. Self- calibration methods will be developed and used for radiation-hard designs whereby threshold voltage shifts due to total dose effects will be automatically compensated. Test structures will be fabricated to explore various design techniques and for the final PLL design. Initial prototyping will be done in the Honeywell MOI-5 process.

RF, Analog and Digital Array for Radiation-Hardened Communication Circuits

University-Industry Team: Carl Sechen and Larry McMurchie (University of Washington) with Andy Peczalski (Honeywell)

Project researchers will develop a reconfigurable radio frequency (RF), analog and digital array for radiation-hardened wireless communication circuits. Our circuits will be programmable at two levels: coarse-grained and fine-grained. Coarse-grained programmability will enable the user to swap in or out different RF, analog, and digital blocks depending on the current needs of the wireless communication system. In addition, one or more digital functional units will contain very high speed field-programmable digital blocks, which will enable customization of various components in the digital signal processing portion of the wireless communication system.

This proposal does not address the design of the analog functional units. Instead, project investigators will leverage these designs from other AFRL/CDADIC researchers. However, the RF and analog functional units will be included in this programmable wireless communication system. The user will be able to programmably interconnect any of the RF and analog functional units along with the digital blocks. In addition to a programmable interconnect between digital and analog/RF blocks, some of the digital blocks will be internally programmable.

Radiation hardness of the programmable wireless communication system will be strongly addressed. In particular, the programmable interconnect between the functional units will be made robust to anticipated SEUs. Also, Honeywell’s SEU-hardened flip-flops and memories will be used. To ensure correct operation of the digital combinational logic units with respect to SEUs, researchers will triplicate these blocks and use majority functions to determine the correct outputs. The majority functions will be embedded as part of the programmable interconnect, so as to minimize any impact on delay. It will be demonstrated that Output Prediction Logic (OPL) is able to withstand total dose radiation at comparable levels to static CMOS. Since the radiation hardness of the RF and analog functional units will be addressed by other AFRL/CDADIC researchers, we anticipate the ultimate design of a reconfigurable, radiation-hardened wireless communication system.

Design of Radiation-Hard Analog/Mixed Signal Circuits in Silicon-on- Insulator Technology

University-Industry Team: S. Subramanian and Gabor Temes (Oregon State University) with Andy Peczalski (Honeywell)

The purpose of this project is to develop novel programmable architectures, circuitry, and design methodologies for radiation-hardened, low-power, analog-digital interfaces in silicon-on-insulator (SOI) technology. This goal will be pursued through a systematic successive development of a number of intermediate stages. In the first year, investigators will focus on a range of primitive analog circuit blocks including amplifiers, buffers, current mirrors, comparators, and sample-and-hold stages. The design optimization will be performed through circuit simulations using a BSIMSOIv3.0 device model combined with device level simulations. The impact of both SOI-specific device issues and radiation tolerance requirements on circuit performance will be investigated. Issues related to total dose effects, dose rate effects, and single event effects will be addressed in radiation hardening considerations. Single event effects (SEE) in analog circuits may manifest in a variety of ways depending upon the circuit, and hence, new methods to characterize them will be developed.

This research will be performed in partnership with Honeywell. In the first year, the devices will be designed for fabrication in Honeywell’s RFSOI (MOI5) technology. Researchers will also perform radiation characterization of test structures fabricated in Honeywell’s radiation-hardened RHSOI process. By combining radiation test results on RHSOI devices and circuit performance fabricated in MOI5 process, investigators will be able to design more advanced radiation-hardened structures to be fabricated in RHSOI process (subject to ITAR limitation) in the subsequent years. We also plan to develop laser testing of single event effects in analog/mixed signal circuits using University of Oregon picosecond laser facility in the future years, subject to the availability of fun