Description of Projects Funded
2003-2004

ESD Padframe Design for Mixed-Signal Baseband IC Cores Through Layout  Extraction and Network Simulation
R. Bruce Darling (University of Washington)

High-Frequency VCO-Based Delta-Sigma ADC in SiGe
Terri Fiez (Oregon State University)

A Low-Cost CMOS Zero-IF Receiver for 5.6 GHz ISM Band Applications
Deuk Heo (Washington State University)

SiGe Data Converter Circuits

George La Rue (Washington State University)

High-Speed A/D Converters in Low-Voltage CMOS Processes
Adrian Leuciuc (State University of New York at Stony Brook)

Multiple Antennas for Ultra-Wideband Wireless Systems: Architecture, Block-Level Circuit Models, Simulations, and Optimization
Huaping Liu (Oregon State University)

Low-Voltage Analog Circuits in CMOS Technology
Un-Ku Moon (Oregon State University)

Low Power Digital IC Design
Carl Sechen (University of Washington)

High-Performance Delta-Sigma Converters
Gabor Temes (Oregon State University)

On-Chip Interconnect Models for High-Frequency/Speed Integrated Circuits on Silicon Substrate
Andreas Weisshaar (Oregon State University) 

 

AFRL Projects

 

Reconfigurable RF Circuits for Low-Cost Phased Array Systems

 David Allstot  (University of Washington) with Greg Kromholtz and Gary Nelson (Boeing)

SOI-CMOS Radiation Total Dose Devise Models for Aerospace Environment Applications
R. Bruce Darling (University of Washington) with Fong Shi (Boeing)

Direct Digital Frequency Synthesizer for Reconfigurable Communication Systems
George La Rue (Washington State University ) with Fong Shi (Boeing)

SOI CMOS Continuous-Time Delta-Sigma A/D Converters for Space Communication Radio Receivers 
Adrian Leuciuc (State University of New York at Stony Brook ) with Bruce Ohme (Honeywell)

Radiation-Hard PLL Design Tolerant to Noise and Process Variation
Un-Ku Moon and Karti Mayaram (Oregon State University ) with Paul Bauhahn (Honeywell)

Low Temperature RF Characterization and Design of MOI5 SOI CMOS Circuits and Devices
Mohamed Osman and Deuk Heo (Washington State University) with Andy Peczalski (Honeywell)

RF, Analog and Digital Array for Radiation-Hardened Communication Circuits
Carl Sechen and Larry McMurchie (University of Washington ) with Andy Peczalski (Honeywell)

Radiation Hardening by Design for Data Converters
Gabor Temes (OSU) with Andy Peczalski (Honeywell)

CDADIC Funded Projects, 2003-2004

ESD Padframe Design for Mixed-Signal Baseband IC Cores Through Layout Extraction and Network Simulation

Principal Investigator:  R. Bruce Darling (University of Washington)
Participating Students:  Yeshwant Subramanian

The overall goal of this project is to demonstrate a ‘full chip’ approach to the design of ESD padframes, primarily for mixed-signal baseband IC cores, through layout extraction and network simulation. In the first two years of this project (2000-2002), the key foundation work involving the development of compact models (including new mathematical techniques) for breakdown processes in semiconductor PN junctions was completed. In the third year (2002-2003), the above models were more fully validated against measurements and enhanced using device simulations, as well as being applied to develop a compact breakdown model for the parasitic BJT in ICs. Additionally, layout extraction routines were tested on a commercial IC (Intersil ISL6207). In the coming year, all of the above tools and models will be put to test by applying them to demonstrate a "full chip" predictive design approach for ESD padframes for mixed signal baseband IC cores.

The predictive simulation based approach to the design of ESD padframes through layout extraction and network simulation can provide a simple and fast methodology for designing custom padframes for ICs in new technologies. In the coming year, the researchers propose to apply the extraction and parameterization routines together with the breakdown models developed in previous years to the design of ESD padframes for mixed-signal baseband IC cores, and to demonstrate the design of new ESD padframe designs through layout, extraction, simulation, and subsequent test chip fabrication. For the first time, the simulation of the entire IC under ESD test conditions and its subsequent comparison to experiment is expected to be carried out. Several padframe design issues that are less easy to address in a hand-design approach will be considered prior to fabrication. It is hoped that this approach could potentially lead to the combination of the design of the core and the padframe into a single design flow, and enable the full-chip design of ESD padframes.

FUNDING: $60,000

High-Frequency VCO-Based Delta-Sigma ADC in SiGe

Principal Investigator:  Terri Fiez (Oregon State University)
Participating Students:  Manu Mishra

The performance bottleneck of most mixed-signal systems is the A/D converter. The focus of this project is to develop a new ADC architecture and demonstrate its performance by implementing it in a SiGe technology. The project emphasis will be on developing an ADC with up to 200MHz clocking frequency and a 35MHz bandwidth. The ADC will leverage the researcher’s previous work where a multibit delta-sigma architecture was developed that used a voltage-controlled oscillator (VCO), rather than a conventional quantizer. Using this architecture as a starting point, the researchers will explore how to optimize it for very high frequency and wide bandwidth operation. The target resolution is up to 10-14 bits in the 35MHz bandwidth. The signal bandwidth can be adjusted to suit the particular application. One unique feature with the VCO-based quantizer is that it provides noise shaping at low frequencies.

FUNDING: $50,000

A Low-Cost CMOS Zero-IF Receiver for 5.6 Ghz ISM Band Applications

Principal Investigator:  Deuk Heo (Washington State University)
Participating Students: Mallesh Rajashekharaiah

FUNDING: $55,000

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SiGe Data Converter Circuits

Principal Investigator:  George La Rue (Washington State University)
Participating Students: Ruiyuan Zhang

This project will investigate high-speed data converter circuits in SiGe BiCMOS technology. The focus of the research will be to increase accuracy of analog-to-digital converters (ADCs) with conversion rates in the 300 MSps to 3 GSps range. These ADCs have applications in high-bandwidth communications and instrumentation. The initial track and hold amplifiers (THAs) determine the overall linearity of many Nyquist ADCs. This research will concentrate on improving the accuracy of the THAs during the next year. Our THA performance goals are 12-bit accuracy at 1 GSps and up to 14 bits at 300 MSps.

THAs using various techniques and architectures will be implemented on the same SiGe wafer and performance measurements will provide a direct comparison between the different approaches. A novel THA design will be implemented that that uses FET-input amplifiers to reduce droop at the hold capacitor. This will be combined with a technique to use the Miller effect to increase the effective capacitance in hold mode for reduced feedthrough. In addition, the characterization of clock and data recovery (CDR) circuits that was designed this year will be completed. A PLL with a lower complexity, phase-frequency-magnitude detection circuit will also be designed, fabricated, and characterized.

FUNDING: $60,000

High-Speed A/D Converters in Low-Voltage CMOS Processes

Principal Investigator: Adrian Leuciuc (State University of New York, Stony Brook)
Participating Students: Ovidui Carnu and Yi Zhang

This project focuses on the development of low-voltage, high-speed data converters implemented in standard and mixed-signal CMOS processes. As one of the bottlenecks of low-voltage mixed-mode IC design is represented by the availability of true low-voltage analog circuitry, our research is proposing new circuit design techniques to override the limitations of deep sub-micron CMOS technology that are encountered in the design of analog cells. Two major goals will be pursued in this project: 1) the development of a wide bandwidth, continuous-time Delta-Sigma modulator; and 2) the design of a high-speed A/D converter using folding, interpolation, and averaging techniques.

The proposed target for the Delta-Sigma modulator is a maximum SNDR of 75dB (equivalent to 12.5-bit resolution) at a bandwidth of 2.5MHZ and using a single supply voltage of 1.8V. As previously reported in earlier CDADIC research, continuous-time DS modulators dissipate less power than their equivalent SC counterparts; these researchers expect to achieve less than 5mW power consumption for their circuit. For the folding and interpolating A/D converter, the target is 10 bits at 100Msamples/sec using a single supply voltage of 2.5V.

FUNDING: $55,000

Multiple Antennas for Ultra-Wideband Wireless Systems: Architecture, Block-Level Circuit Models, Simulations, and Optimization

Principal Investigator:  Huaping Liu (Oregon State University)
Participating Students: Shiwei Zhao and Joy Gao

Researchers of this project will study multiple-input multiple-output (MIMO) antennas for ultra-wideband (UWB) systems. UWB technology has a number of extremely attractive features, including high-data-rates over short distances (typically within 10-20 meters). The large block (3.1-10.6GHz) of unlicensed "free"spectrum through overlay with existing narrowband radios will open up a new spectrum of wireless applications. However, will be demonstrated, the multipath delay spread of the UWB channel severely limits the achievable data rates necessary for future-generation broadband multiple-access wireless applications (e.g., HDTV plus high-speed Internet access). MIMO systems are capable of providing great spectral efficiencies and can be combined with UWB technique for robust and high-rate communications. With today’s antenna design technology, it is feasible to implement up to three-to-four relatively independent antennas in a small handheld device (e.g., a PDA).

The research proposed under this project encompasses novel system architecture, new low-complexity signal processing techniques, modeling of mixed-signal and RF circuit blocks, and development of simulation tools. The research will help companies involved in the design of communication circuits and systems to efficiently explore new market opportunities in the promising area of broadband wireless communications.

FUNDING: $60,000 

Low-Voltage Analog Circuits in CMOS Technology

Principal Investigator:  Un-Ku Moon (Oregon State University)
Participating Students:  M. Keskin, D. Chang, J. Li, G. Vemulapalli, K. Lee, G. Ahn 

Thus far, this low-voltage (LV) analog circuits research has focused on the implementation of a LV bandpass delta-sigma modulator, pipelined/algorithmic ADCs, and precisely-tuned, continuous-time filters. The main thrust in this research has been to develop new circuit techniques that would operate within maximum voltage limits of future state-of-the-art CMOS technologies, and new digital calibration techniques for various pipelined ADC architectures. One of the novel low-voltage switching techniques developed under this research involved using opamp in its unity-gain feedback mode to allow operation without use of floating switches. Research this year will continue work in this are of low-voltage analog circuits in CMOS. The continuing low-voltage topics include high-resolution, self-calibrating ADCs and multi-bit multi-stage algorithmic/pipelined ADCs.

FUNDING: $60,000

Low Power Digital IC Design

Principal Investigator:  Carl Sechen (University of Washington)
Participating Students:  Miodrag Vujkovic, Duncan Lam, Hiran Tennakook 

Project researchers plan to continue their work to refine a fully automated digital IC design flow that fully minimizes power consumption for a user-specified level of performance (delay or throughput). Both DSP and control logic blocks, or any combination, are optimized in the approach. Dramatic power reductions (2X-3X) are achieved, compared to the leading EDA tools, for the same level of circuit performance.

In this work, flow proceeds all the way from Verilog/VHDL to layout. An interesting feature of this project’s flow is that it eliminates the timing closure problem, while requiring no timing driven placement or routing tools. The approach is based on transistor sizing, VDD optimization and a novel approach to placement and routing, as well as foundry-independent cell generation. The researchers will also trace out the complete power versus delay curve for a circuit, post-layout.

FUNDING: $55,000 

High-Performance Delta-Sigma Converters

Principal Investigator: Gabor Temes (Oregon State University)
Participating Students: Xuesheng Wang, Jose Silva, and Yuhua Guo

Fast and accurate analog-to-digital converters (ADCs) are needed in many important applications, including high-definition digital video, digital subscriber lines, and software radio architectures. This project is aimed at the development of delta-sigma ADCs with specifications that satisfy such stringent requirements.

Specifically, this project will derive design techniques for high-speed, high-accuracy ADCs realized in standard CMOS technology. The specific target numbers are 25 MS/s data rate and 16 bits resolution. To achieve such high accuracy, delta-sigma conversion is indicated; however, the high data rate limits the oversampling ratio (OSR) to below 10. At such low OSR, special configurations are needed to obtain the required quantization noise suppression. Simulations indicated that a suitable architecture is the 2-2-2 MASH one, with multibit quantizer in all stages. This structure relies on a combination of noise shaping, reduced quantization errors and error cancellation to limit the quantization noise in the overall output. However, the first-stage internal DAC must be linear to within 1/2 LSB of the 16-bit output, and the error cancellation between analog and digital paths needs to be comparably accurate. Since the component matching accuracy is only about 10 bits, and the opamps used also limit the accuracy of the analog error path, these requirements are not directly achievable.

FUNDING: $60,000

On-Chip Interconnect Models for High-Frequency/Speed-Integrated Circuits on Silicon Substrate

Principal Investigator:  Andreas Weisshaar (Oregon State University)
Participating Students: Amy Luoh, Yevgeniy Mayevskiy, and Rajarajan Senguttuvan

The overall objective of this project is the development of efficient CAD-oriented models for on-chip interconnects and passive components, such as spiral inductors, for modern silicon-based RF, high-speed analog, and mixed-signal ICs. In previous research, investigators focused on the development of physics-based, closed-form expressions for the frequency-dependent interconnect parameters including substrate loss, and skin and proximity effects in the metalization. In the next phase of this project, a new compact lumped-element modeling methodology will be developed. In the proposed general automated modeling approach, lumped element values are extracted from given S-parameter data while taking into account user-supplied information such as circuit topology or partly known parameter values.

FUNDING: $60,000

AFRL Funded Projects, 2003-2004

 

 

Reconfigurable RF Circuits for Low-Cost Phased Array Systems

University-Industry Team: David Allstot (University of Washington) with Greg Kromholtz and Gary Nelson (Boeing)

The demand for higher performance RF integrated systems motivates the development of low-cost single-chip phased-array communications system-on-chip solutions operating at 15 GHz and above. Concerns about coupling between transmit and receive channels are mitigated by adopting a simplex architecture including the on-chip digital command and control circuitry. Hence, in contrast to previous attempts at sub-system integration, this work aims to develop a complete single-chip solution that enables low-cost high-volume in a SiGe BiCMOS technology for chip-on-board simplex phased-array communications systems in a small physical size and low weight antenna assembly.

Successful integration of the simplex transceiver at 15 GHz requires significant circuit innovation. A major aspect of this research is the investigation of novel low-loss RF T/R switch architectures. Another important circuit component is a precision RF digitally controlled phase shifting network. Our aim here is to provide tuning functions so that the RF switch loss and phase network accuracy exhibit minimum variation to process, voltage, and temperature variations in the IBM 0.25µm SiGe 6HP BiCMOS process. In other words, techniques to maximize the manufacturability and minimize the cost are of paramount importance. Other major circuit blocks to be developed include a variable-gain low-noise amplifier and a high-efficiency power amplifier suitable for use with DQPSK coding.

 

SOI-CMOS Radiation Total Dose Device Models for Aerospace Environment 

University-Industry Team: R. Bruce Darling (University of Washington) with Fong Shi (Boeing)

The objective of the research is to methodically develop improved device models for submicron SOI MOSFETs which include the primary effects of the space environment. The scope of the present work includes temperature effects over the range of -65ºC to +200ºC, the immediate effects of ionizing radiation on SOI MOSFET device characteristics, and the prolonged, long-term effects of total radiation exposure doses. The outcome will be a novel and improved SPICE SOI MOSFET model which can be used in standard circuit simulators to assess the functionality and robustness of a circuit design to the temperature and radiation extremes of space. Rather than to develop a new MOSFET circuit simulation model from scratch, the plan of this research work is to start from the extensively developed and widely accepted Berkeley short-channel insulated gate MOSFET model, or BSIM, which is the presently the standard for integrated circuit simulation. This model has recently been extended to the case of SOI as BSIM3SOI, and its source C-code is publicly available.

Another objective of the research is to encapsulate the majority of the radiation physics within the internal code of the simulation model, so that it can be used by circuit designers much like any other SPICE MOSFET model. There exist numerous SPICE macro-modeling techniques to deal with unique device-circuit interactions and physical effects. However, for a circuit of even modest size, these macromodeling techniques rapidly become cumbersome and error-prone due to their awkward implementation, mixed dimensional units, and vague subcircuit boundaries that cut across different physical domains. The creation of an externally clean MOSFET model for circuit simulation will allow a simpler simulation interface and should reduce errors that are common to the intricacies of macro-modeling.

Direct Digital Frequency Synthesizer for Reconfigurable

Communication Systems

University-Industry Team: George La Rue (Washington State University) with Fong Shi (Boeing)

This project continues the investigation of direct digital frequency synthesizers (DDFSs) in silicon-on-insulator (SOI) CMOS technology for space applications. DDFSs provide very fast frequency hopping, low-phase noise and high frequency resolution, which are important requirements for many modern wireless communication systems. DDFSs are more versatile than VCO based synthesizers and are reconfigurable after deployment to meet a wide variety of applications. This is important for space applications where the life of a mission can be very long, requirements may change and replacing electronics after deployment is usually not an option. Binary DAC and nonlinear DAC approaches have been investigated for the implementation of DDFSs. The complexity of the non-linear DAC approach was much less than the binary DAC approach and was selected for fabrication. This approach implements a 32-segment piecewise linear approximation to the sinusoid and the lookup table is implemented as 19 16:1 multiplexers. Honeywell’s radiation-tolerant MOI5 0.35 mm SOI CMOS process is being used to implement the non-linear DAC DDFS. The phase accumulator is currently limiting operation of the DDFS to about 1.6 GHz. Layout is almost complete. During the next year, an improved version of the DDFS will be designed, fabricated and characterized. Improvements include adding a quadrature output, increasing resolution by 2 bits, lowering power dissipation, fully automating the digital trimming and adding continuous calibration circuitry for differential outputs.

SOI CMOS Continuous-Time Delta-Sigma A/D Converters for Space Communication Radio Receivers

University-Industry Team: Adrian Leuciuc (State University of New York at Stony Brook) with Bruce Ohme (Honeywell)

Project researchers are developing analytical methods allowing us to predict the response of some analog cells to single-event effects. The approach is based on the fact that for the class of considered analog circuits the time constants associated to them are much larger than the duration of the charge generation process in the substrate of a SOI device and therefore this effect can be approximated by a Dirac impulse. The team is quite advanced in obtaining an operational algorithm to predict the single-event upset for comparators as a function of the particle Linear Energy Transfer (LET) parameter and hit location. To our knowledge, no attempts have been made in this direction and for the next year our plan is to extend this approach to other analog cells. However, the accuracy of the proposed method depends on the accuracy of SOI MOSFET models and the research team will try to validate the correctness of the proposed single-effect model by carrying out device level simulations. The ECE department of Stony Brook University has license for ISE-TCAD, a software tool used for 2D and 3D device simulations and which has the capability to simulate heavy ion hits and to predict the ionization effect and the way the electron-hole pairs are eliminated from the substrate of the hit device.

During this year the theoretical predictions of radiation effects will be experimentally verified on prototypes of delta-sigma modulators fabricated in Honeywell’s MOI-5 process. The PI’s university is located close to and has strong connections with Brookhaven National Laboratory and one intend to use the lab’s heavy ion testing facilities to characterize the fabricated prototypes. Besides this type of testing, we also intend to use pulsed laser excitation to simulate the ionization effect produced by heavy ion hits. Laser excitation will allow us to identify the most sensitive blocks in the entire system.

Radiation Hard PLL Design Tolerant to Noise and Process Variation

University-Industry Team: Un-Ku Moon and Karti Mayaram (Oregon State University) with Paul Bauhahn (Honeywell)

This project addresses the design of radiation-hard and noise-tolerant, phase-locked loops (PLLs) for frequencies greater than 1GHz in the Honeywell 0.35um SOI CMOS (MOI-5) process. The overall focus is on a systematic design methodology for radiation-hard, noise tolerant PLLs in SOI CMOS processes. New circuits and architectures will be developed and combined with self-calibration methods. The self-calibration methods will enable tuning out process, temperature, threshold voltage, and supply voltage variations yielding a robust design. Layout and/or backbias techniques will be used to compensate for the radiation-induced leakage if it cannot be accommodated by adaptive circuit techniques. Floating-body devices will be compared with body-tied devices in the context of the PLL design and their effect on the PLL jitter/phase noise performance will also be evaluated.

The research focus will be on two of the key building blocks of a PLL. These are the charge-pump based loop filter, and the voltage controlled oscillator (VCO). The SOI specific issues that will be addressed are the floating body, kink effect, and self heating. Both LC and ring type of VCO architectures will be implemented for a fully integrated solution of the PLL. Self-calibration methods will be developed and used for radiation hard designs whereby threshold voltage shifts due to total dose effects will be automatically compensated for. Test structures will be fabricated to explore various design techniques and for the final PLL design. Initial prototyping will be done in the Honeywell MOI-5 process.

Low Temperature RF Characterization and Design of MOI5 SOI CMOS Circuits and Devices 

University-Industry Team:  Mohamed Osman and Deuk Heo (Washington State University ) with Andy Peczalski (Honeywell)

The project focuses on low temperature characterization and design of a readout block of IR gray scale image sensor for operation at 77K possibly in radiation environment. This will involve RF and DC characterization of SOI CMOS devices and components at 85K to: (a) develop the models required for circuit design; (2) determine noise parameters, (3) effect of radiation on noise and device parameters. Prototype circuits will be designed using the measured model parameters. These include: (1) focal plane readout and (2) RF upconverter with immunity to the noisy power lines. These circuits are essential building blocks for future ultra-low power IR imaging sensor arrays. The design will focus on minimizing the power consumption by minimizing the number connections between the sensor chip operating at 77K and the power supply and image processing components of the sensor. It will involve transmission of image gray scale analog signals to an off chip ADC to minimize power dissipation. Two modes of image signal transmission will be explored: (1) using power supply lines and (2) wireless transmission. Selected components such as MOSFET, diodes, passive elements, and circuits will be evaluated for low temperature operation and radiation conditions. The model parameters and noise performance will be determined from DC and RF measurements down to 85K using the characterization facilities at WSU. This proposal addresses two areas of interest: ultralow-power technologies and standard cell topologies in radiation-hardened SOI.

 

RF, Analog and Digital Array for Radiation-Hardened Communication Circuits

University-Industry Team: Carl Sechen and Larry McMurchie (University of Washington) with Andy Peczalski (Honeywell)

We are proposing a scope of work that will accomplish two goals. The first goal is a better understanding of the effects of radiation, particularly Single Event Effects (SEUs), on both digital and mixed-mode circuits. While the effects of radiation on RAM cells has been thoroughly studied and numerous remediation techniques proposed, SEUs or Single Event Transients (SETs) have not been widely studied. Few remediation techniques other than TMR-in-hardware have been proposed. The second goal is the development of a coarse-grained reconfigurable analog/digital architecture. We believe that such a reconfigurable architecture has a large power/speed/area/functionality advantage over existing fine-grained commercial FPGAs.

Radiation Hardened by Design for Data Converters

University-Industry Team: Gabor Temes (Oregon State University) with Andy Peczalski (Honeywell)

The long-term goal of this research is to use hardening-by-design (HBD) methodology for the development of analog-to-digital as well as digital-to-analog data converters. A key feature will be the use of digitally-corrected analog circuitry and implementation methodologies. Specialized layouts as well as circuit techniques will be utilized to achieve robustness against radiation effects, while using only inexpensive commercial CMOS technology. A state-of-the-art DAC will developed, using novel radiation-hardened analog and digital stages and building blocks. The impact of both CMOS device issues and device-level radiation effects will be studied on the performance of these circuits. A special design technique, which will be incorporated in the analog circuits, involves the use of digital correction to monitor and overcome the effects of parameter variations due to radiation exposure. This project will be followed by similar work on rad-hardened delta-sigma ADCs.