Calibration Techniques for Low-Voltage, Low-OSR Sigma-Delta ADCs for Communication Applications
David Allstot (University of Washington)

Advanced Padframe Design for Mixed-Signal CMOS
R. Bruce Darling (University of Washington)

High Frequency Delta-Sigma ADCs
Terri Fiez (Oregon State University)

Low-Voltage and Highly Linear CMOS RFICs for Advanced Communications
Deuk Heo (Washington State University)

Ultra-Low Ripple Step-Down Switched-Capacitor Voltage Converters
Annette von Jouanne (Oregon State University)

SiGe Data Converter Circuits

George La Rue (Washington State University)

Reconfigurable Delta-Sigma Modulators for Multi-Mode Wireless Communications
Adrian Leuciuc and Alex Doboli (State University of New York at Stony Brook)

Low-Voltage Analog Circuits in CMOS
Un-Ku Moon (Oregon State University)

High-Performance Delta-Sigma Converters
Gabor Temes (Oregon State University)

On-Chip Interconnect Models for High-Frequency/Speed Integrated Circuits on Silicon Substrate
Andreas Weisshaar (Oregon State University) 

NSF TIE Project: Linearization Techniques for RF Power Amplifiers
David Allstot (University of Washington)

AFRL Projects

 

Reconfigurable RF Circuits for Low-Cost Phased Array Systems

 David Allstot  (University of Washington) with Greg Kromholtz and Rod Bonebright  (Boeing)

Circuit Design Techniques for Low-Voltage, Analog CMOS Integrated Circuits for Extreme Environments
Benjamin Blalock (University of Tennessee) with David Hogue (Boeing)

Adaptive Regulation and Logic for Subthreshold Circuits
Lawrence Clark (Arizona State University ) with Intel

Radiation-Tolerant SiGe BiCMOS Smart MMICs for Space Communications
Deuk Heo (Washington State University ) with Fong Shi (Boeing)

Direct Digital Frequency Synthesizer for Reconfigurable Communication Systems
George La Rue (Washington State University ) with Fong Shi (Boeing)

SOI CMOS Continuous-Time Delta-Sigma A/D Converters for Space Communication Radio Receivers 
Adrian Leuciuc and Alex Doboli (State University of New York at Stony Brook ) with Bruce Ohme (Honeywell)

Radiation-Hard PLL Design Tolerant to Noise and Process Variations
Un-Ku Moon and Karti Mayaram (Oregon State University ) with Andy Peczalski (Honeywell)

RF, Analog and Digital Array for Radiation-Hardened Communication Circuits
Carl Sechen and Larry McMurchie (University of Washington ) with Andy Peczalski (Honeywell)

Radiation Hardening by Design for Data Converters
Gabor Temes (OSU) with Andy Peczalski (Honeywell)

CDADIC Funded Projects, 2004-2005

Calibration Techniques for Low-Voltage, Low-OSR Sigma-Delta ADCs for Communication Applications

Principal Investigator: David Allstot (University of Washington)

Participating Student: Jeyanandh Paramesh

        The rapid proliferation of wireless communication devices and standards has been driven in large part by Moore’s law, according to which the availability of digital processing capability for a given power constraint doubles roughly every 18 months. Modern wireless communication devices leverage this capability by using sophisticated signaling and coding schemes; examples of this include MIMO-OFDM systems and newer coding techniques that allow the system to operate closer to the Shannon limit at the expense of complex demodulation and decoding requirements. Additionally, channel bandwidths have also been increasing leading to higher data rates and network throughput. In currently evolving communication standards, the signal to be digitized occupies an ever-increasing bandwidth. Furthermore, implementation of high-precision analog systems, of which the ADC is an example, has become more challenging due to the downward scaling of voltage headroom and its associated consequence of lower gain. It thus becomes necessary to use digital processing capability to correct for analog imperfections digitally. Sigma-delta (Σ∆) ADCs were identified in the mid-eighties for their robustness when implemented in digital CMOS technology; they traditionally used large over-sampling ratios (OSR) to digitize low-bandwidth signals with 16-20 bits of resolution. More recently, sigma-delta ADCs have been realized with low over-sampling ratios of 4-16X. Consequently, these architectures have begun to encroach on the speed-resolution space traditionally occupied by Nyquist-rate pipeline converters. We note that the basic requirement of oversampling above the Nyquist is not a bottleneck in many applications. In many highly integrated systems, a low oversampling ratio is often used to alleviate the specification on the anti-aliasing filter.                               

FUNDING: $45,000

 

 

Advanced Padframe Design for Mixed-Signal CMOS 

Principal Investigator: R. Bruce Darling (University of Washington)

Participating Student: T. Christiansen

Modern integrated circuits have pad frame designs which limit their signal fidelity and which create reduced bandwidth with the addition of bonding wire inductances and ESD/EOS protection device capacitances. The proposed research plans to develop a means for improved characterization of these I/O pads on the pad frame by means of layout extraction and compact device modeling, much of which has already been developed for ESD system simulation. In addition, a novel on-chip sampling system will be developed to provide model validation. New pad frame circuits will be developed to produce better optimized trade-offs between ESD/EOS protection levels and the reduction in signal integrity and bandwidth capabilities. Frequency dependent grounding and passive compensation networks will both be used as a design strategy in this pursuit. The objective of this project is to develop new pad-frame designs for mixed-signal CMOS ICs that provide wide band signal feed-through integrity which is not corrupted by excessive parasitic elements and simultaneously good survivability to electrostatic discharge (ESD) and other electrical overstress (EOS) conditions.

Potential member company benefits: The outcome should be a better understanding of the trade-offs in high-performance mixed-signal pad-frames, as well as several example pad-frames that interested member companies could try out for themselves.

FUNDING: $49,000

 

 

High Frequency Delta-Sigma ADCs

Principal Investigator: Terri Fiez (Oregon State University)

Participating Student:  Zhimin Li

Oversampling -Σ A/D converters were traditionally and are still widely used for low-frequency, medium-to-high resolution applications, such as instruments, audio, and voice. In the last decade, there has been a growing trend in wireless and wireline communications to move analog-to-digital conversion towards the system frontend. This implies that more signal processing is shifted from the analog domain to the digital domain. As a result, high-performance digital systems can be realized and the advancement in digital CMOS processes can be fully utilized. However, as the interface between analog and digital data, A/D converters have to provide higher dynamic range to accommodate weak analog input signals accompanied by significant noise and interference. Therefore, designing -Σ A/D converters with MHz signal bandwidths and more than 14-bit dynamic range is a challenging topic for both industry and academia. To date, most reported MHz range -Σ A/D converters are implemented with switched-capacitor (SC) techniques, mainly due to its mature design methodologies and robustness. -Σ A/D converters employing SC techniques are also commonly referred to as discrete-time (DT) converters. However, recently, continuous time (CT) -Σ A/D converters have attracted more and more interest. Compared with DT converters, CT converters have the advantages of lower power consumption and intrinsic anti-aliasing filtering. Moreover, absence of stringent settling requirements enables CT converters to digitize up to several hundred MHz input signal, which is still impossible for their DT counterparts. This research targets at a 14-bit dynamic range, 2.5-MHz input signal bandwidth (equivalently, 5MSPS) -Σ A/D modulator by using continuous-time design techniques. The modulator with such specifications can find application in wideband wireless, wireline communication systems, high-speed scientific instruments, medical imaging and vibration analysis.

Potential member company benefits: The techniques we are developing are applicable to other mixed-signal circuits. Additionally, we expect other novel circuit techniques will be developed as we work through the design.

FUNDING: $44,000

 

 

Low-Voltage and Highly Linear CMOS RFICs for Advanced Communications

Principal Investigator:  Deuk Heo (Washington State University)

Participating Students:  Parag Upadhyaya and Mallesh Rajashekharaiah

Design of linear and low power CMOS RF circuits at low voltage has not been fully investigated. Our intention is to sidestep the weakness of CMOS technology at the architectural level and investigate innovative solutions for RF circuits that function well at low supply voltage. During the previous  CDADIC funded period, a dual-gain low noise amplifier incorporating a novel gain-controllable active balun and a new sub-harmonic mixer were designed for a 5.6 GHz direct down conversion receiver (DCR) in 0.25-_m technology node. These novel circuit topologies combined to make a low cost and compact DCR. The LNA operating in two gain modes with 19.5dB and 12.8dB gain provides low noise figures of 3.1 and 3.5 dB respectively in the high and low gain modes. The direct down conversion mixer achieves an IIP2 of more than 55 dBm and IIP3 of more than -7dBm while achieving 8 dBm of gain. In the coming year, our research will be aimed at the design of integrated low-cost, low voltage, highly linear CMOS RF sub-circuits for a low- and zero-IF transceiver for ISM band applications using 0.18-µm CMOS technology. The proposed project has two major thrusts (i) Investigation of low voltage solution for wireless receiver sub-components, namely, down-conversion mixer with high IIP3 and IIP2 values, low noise amplifier (LNA) with high gain and wide dynamic range, and half-rate quadrature LC VCO; (ii) Investigation of wireless transmitter sub-components which includes up-conversion mixer with good linearity and P1dB, RF switch with high isolation and low insertion loss, and preliminary research for linear drive/power amplifiers. These sub-circuits will be a basis for low voltage and high linear RFICs for various ISM band communications.

Potential member company benefits: The reconfigurable SPDT switch will be an ideal alternative to conventional LC resonant T/R switches to achieve high isolation and power handling while providing a tuning option for a fully integrated SoC solution. Furthermore, with the emergence of MIMO systems such a switch holds immense potential. Receiver linearity has been the prime focus of industry-backed research and highly linear LNA and mixer components in low-voltage scaled CMOS technology will be a positive and appreciable step towards high performance low-cost integrated CMOS transceivers. Low voltage and low power quadrature VCO with low phase noise and more importantly low quadrature phase error will help mitigate performance degradation that in many cases are the bottle neck for DCR and image reject receivers. This research will greatly benefit member companies in transceiver application as well as companies interested in clock generation and PLLs. 

FUNDING: $54,000

 

 

Ultra-Low Ripple Step-Down Switched-Capacitor Voltage Converters 

Principal Investigator: Annette von Jouanne (Oregon State University)                                    

Participating Student:  Jifeng Han

Rapidly dropping power supply voltages and tight voltage regulation requirements for integrated circuits challenge power supply designers. A novel interleaved discharging (ID) approach is proposed to reduce the output ripple in step-down switched-capacitor (SC) dc-dc converters. Preliminary simulation and experimental results from a four-stage SC dc-dc converter show that the ID approach can reduce the output ripple by a factor of three. The proposed ID approach also improved the converter efficiency by 7%. The ID approach is suitable for all step-down SC dc-dc converters and provides flexibility in optimizing the design of SC dc-dc converters. This research focuses on the investigation of ultra-low ripple step-down (buck) switched-capacitor voltage converters (also known as charge pumps). The ultimate goal is to achieve an output ripple N times lower than that of a conventional N-stage buck charge pump, along with improved efficiency. Research directions also include improving line- and load-regulation capabilities of the charge pump.

Potential member company benefits: The proposed ultra-low ripple charge pumps will have many important applications, including power management in wearable electronic devices, e.g., cellular phones, personal digital assistants (PDA’s), digital cameras, and handheld medical instruments. The charge pump developed under this project should be very useful to member companies.

FUNDING: $49,000

 

 

SiGe Data Converter Circuits 

Principal Investigator: George La Rue (Washington State University)

Participating Students: Dirk Robinson Yousu Chen, and Ruiyuan Zhang

This project will investigate high-speed data converter circuits in SiGe BiCMOS technology. The focus of the research will be to increase accuracy of analog-to-digital converters (ADCs) with conversion rates in the 300 MSps to 3 GSps range. These ADCs have applications in high-bandwidth communications and instrumentation. In many Nyquist ADCs, the initial track and hold amplifiers (THAs) determine the overall linearity of the ADC. Work was started this year to improve the accuracy of THAs with goals of 12-bit accuracy at 1 GSps and up to 14 bits at 300 MSps. We are designing several THAs using different architectures and various compensation techniques so that they can be compared using the same SiGe BiCMOS process. These THAs will be laid out, fabricated and tested in the coming year. We will also investigate ADC architectures and implementations to achieve low-power and high accuracy to go along with the THAs. We will investigate methods to use low-cost CMOS trimming circuits to compensate for errors due to process mismatches and non-ideal components in the predominately bipolar ADC building blocks for increased accuracy. We will design, layout, fabricate and test ADC building blocks for pipelined and successive approximation approaches

Potential member company benefits: This work will help to increase understanding the effect different approaches and techniques have on the performance of high-speed high-accuracy THA circuits by a direct comparison of measurements of different THAs implemented on the same SiGe wafer. THAs are key to building high-performance high-linearity ADCs. The accuracy of high-speed ADCs may be increased from methods and techniques developed by this work.

FUNDING: $54,000

 

 

Reconfigurable Delta-Sigma Modulators for Multi-Mode Wireless Communicaitons

Principal Investigator: Adrian Leuciuc and Alex Doboli (State University of New York at Stony Brook)

Participating Students: Ovidiu Carnu, Yi Zhang, Ying Wei

This project proposes a new research topic, the design of reconfigurable DS modulators for multi-mode receivers for wireless communications. The approach the investigators envisage to use is a combination of top-down design for finding the system-level parameters and topologies of the best possible candidates satisfying the specifications for all modes of operation under consideration (AMPS, GSM, CDMA, WCDMA, and UMTS), and a bottom-up approach for optimizing the circuit-level parameters of the implemented systems. The optimization step is based on transient simulations of the complete DS modulators, a task that is computationally intensive, and a new approach to fast time-domain simulation of analog systems that contain nonlinear parameters, previously proposed by one of the investigators, will by used.

Potential member company benefits: Design strategies for reconfigurable continuous-time DS modulators; behavioral models (System C) for the analog cells in such systems.

FUNDING: $49,000

 

 

Low-Voltage Analog Circuits in CMOS

Principal Investigator: Un-Ku Moon (Oregon State University)

Participating Students:  J. Li, G. Vemulapalli, S. Xiao, Y. Kook, P. Kurahashi

            This research effort focuses on developing new circuit techniques suitable for current and future low-voltage submicron CMOS processes. IC solutions are targeted in the area of switched-capacitor circuits,  data converters, and filters. Current research directions include ultra low-voltage analog-to-digital converters and low-voltage continuous-time filters. Accomplishments so far include low-voltage ∆Σ modulators and pipelined/algorithmic A/D converters that use the active opamp-reset switching technique, avoiding the use of floating switches. There are two prototype ICs to be reported on at this Summer meeting. A 0.9V background calibrated ADC has been fully evaluated and presented at VLSI Symposium 2004 (June). The prototype demonstrates 81dB SFDR at 2MSPS while only consuming 12mW. The operation is good to 5MSPS with 4dB degradation. Highly linear and accurately tuned 0.8-V continuous-time filter has been fully evaluated and will be presented at CICC 2004 (October). This work demonstrates a combined performance of ultra low voltage (0.8) and high linearity (-80dB THD). Continuing research includes high spurious-free dynamic range pipelined ADC utilizing opamp sharing and capacitor error averaging schemes, and low-voltage linear switched-R-MOSFET-C filter.

Potential member company benefits: Newly developed low-voltage circuits (e.g. opamp-reset, switched-R-MOSFET-C) that overcome inherent low-voltage limitations may be adopted for future state-of-the-art low-voltage CMOS processes. And a set of practical low-voltage design issues are understood and summarized by this research.

FUNDING: $54,000

High-Performance Delta-Sigma Converters 

Principal Investigator: Gábor Temes (Oregon State University)

Participating Students: Zhenyong Zhang, Yoshio Nishida, and José Silva

            The purpose of this continuing project is to develop novel architectures, algorithms, and design techniques for wideband and high-accuracy ADCs for applications in high-definition video systems, digital subscriber lines and software radios. The research results are to be verified by developing test chips with about 16-bit accuracy and fast (25 MS/s) sampling rates in standard CMOS technology.

Wide-band and high-accuracy analog-to-digital converters (ADCs) are increasingly needed in many consumer products and in telecommunication applications. Since the required resolution may be as high as 16 bits, the most suitable realization is the noise-shaping (delta-sigma) one. However, such converters rely on oversampling for achieving low in-band quantization noise, and hence are inherently slower than other, less accurate, ADCs. Our approach to solving this problem is to utilize high-order delta-sigma loops with multi-bit internal quantization. This makes it possible to achieve high dynamic range even with low oversampling ratios. This approach, however, introduces another problem, that of the inherent nonlinearity of the internal multi-bit DAC. Traditionally, this problem is solved by using a "mismatch-shaping" process, in which the error signals introduced by the DAC nonlinearities are filtered, and suppressed in the signal band. However, mismatch shaping becomes ineffective for low oversampling ratios, which we are forced to use in our applications. Therefore, we have developed alternative techniques, based on digital correlation, to acquire and then cancel the nonlinearity errors of the internal DAC. The general principle is illustrated in Figure 1. Here, b(k) is the digital input signal of the DAC, and v(k) is the digital output signal of the complete ADC. ETF is the digital equivalent of the error transfer function from the DAC to the ADC output. Multiplying v(k) and bi(k), and averaging the products, gives an estimate of the error ei of ith DAC unit element. The accuracy and speed of the process improves if the part of v(k) which is not due to the DAC error is not too large, and is uncorrelated (or only slightly correlated) with the b(k). This was achieved using scrambling, filtering and quantization error cancellation in our previous project.

            Potential member company benefits: Companies which use and/or design wideband and high-accuracy data converters can take advantage of the design techniques developed under this grant.

FUNDING: $49,000

On-Chip Interconnect Models for High Frequency/Speed Integrated Circuits on Silicon Substrate

Principal Investigator: Andreas Weisshaar (Oregon State University)

Participating Students: Joel Kolstad, Chris Blevins, Shruti Mangalmurti, Brian Courts

            This project aims at developing new CAD-model-generation algorithms and tools for on-chip interconnects and passive components that are compatible with commercial circuit simulators and design tools. The electrical performance of interconnects and electronic packaging is becoming a major bottleneck in the overall performance of silicon-based RF, high-speed, and mixed-signal integrated circuits. Furthermore, passive components such as spiral inductors are increasingly integrated on chip. Hence, circuit designers are in critical need of accurate and efficient models for interconnects and passive components for reliable circuit design. Passive elements are traditionally modeled as compact ideal-element circuits because of their inherent physical interpretation, versatility, robustness, and efficiency. At higher frequencies, however, the development of compact equivalent circuit models for passive elements is getting much harder and requires a significant amount of engineering time. On the other hand, purely mathematical “black-box” approaches are more general but can lead to large models and lack physical insight. Our new model generation approach combines the strengths of both modeling worlds. We augment an existing (low-frequency) equivalent circuit model with a lower-order black-box model. As a result, we retain physical insight while making it possible to automatically generate CAD models for an extended frequency range. This new approach is aimed at significantly reducing engineering time spent on model development.

Potential member company benefits: A new automated tool to generate compact CAD models from S-parameters for a wide range of on-chip passive structures and components. The models will accept a user-supplied equivalent circuit model and generate an augmentation network while retaining the equivalent circuit topology with perturbed circuit parameter values.

FUNDING: $54,000

 AFRL Projects, 2004-2005

 

Reconfigurable RF Circuits for Low-Cost Phased Array Systems

University-Industry Team: David Allstot (UW) with Greg Kromholtz and Rod Bonebright (Boeing)

The demand for spectrally efficient communication methods is the motivation behind the development of phased array systems. A phased array system with careful design can offer a low-cost means of increasing the efficient use of currently available bandwidth. Several key focus areas can greatly reduce the cost, for instance, by using a single die, with an integrated T/R switch, there is no necessity of two antennas. By using a silicon process, the cost of the die is decreased. The concerns of on-chip coupling can be mitigated by using simplex operation, thus the TX and RX paths are never on at the same time.

In order to achieve a simplex transceiver on silicon, there is still much innovation necessary. Work completed on this subject in the previous year has greatly enhanced the ability to realize these systems, however, much work still needs to be accomplished. The PA and T/R switch have never been realized on a silicon substrate and implemented in a practical system at 15 GHz. The goal of this research will be to not only design these circuits to meet the specifications, but also to design compensation for variations due to process, voltage and temperature. These techniques developed will be implemented for potential fabrication on the IBM 7HP SiGe BiCMOS process. 

 

Circuit Design Techniques for Low-Voltage, Analog CMOS Integrated Circuits for Extreme Environments 

University-Industry Team: Benjamin Blalock (UT) with David Hogue (Boeing)

        Interest in radiation hardening by design is continuing to increase. Factors motivating this include the high cost of radiation-hardened semiconductor processing compared to standard commercial processing, as well as the technology lag (typically at least one generation) of rad-hard processes behind commercial manufacturing. In addition, the continued scaling of CMOS technology places severe voltage constraints on mixed-signal systems, prompting the need for new analog circuit design techniques to realize systems-on-a-chip on very deep submicron processes. Thus, two great challenges currently facing rad hard mixed-signal design is the lack of available circuit-level hardening by design techniques for analog, and the need for robust analog circuit design techniques compatible with the low voltage constraints of scaled CMOS processes. This work seeks to address both of these issues by: 1) providing a comparative study of analog biasing techniques, including the novel fixed inversion coefficient biasing scheme, to determine the optimal approach for minimizing total ionizing dose (TID) effects and therefore yielding an analog circuit-level hardening-by-design (HBD) approach, and 2) developing a new low-voltage pipeline ADC design utilizing body-driving and characterizing its performance as a function of TID irradiation. 

 

 Adaptive Regulation and Logic for Subthreshold Circuits

University-Industry Team: Lawrence Clark (ASU) with Intel

       Low power system on chip (SoC) designs are increasingly important to diverse applications ranging from hand-held cell phones and PDAs, medical devices such as pacemakers, to military applications including wearable computing and communications, and space systems. Most of the IC’s aimed at such applications must cope with limited battery capacity and thermal capability. Present commercial system on chip (SOC) designs have dozens of supply voltage domains for power savings, SRAM stability, and independent power down capabilities. Based on present trends, even more independent supplies can be expected in the future. This allows lower power, but invites the difficult problem of generating the supply voltages either at the board or die level.

       The research proposed here will develop radiation hardened by design CMOS circuit techniques to allow very low operating voltage, i.e., both in and/or near subthreshold operation with on-die voltage down conversion and high efficiency regulation. Integration with large mixed signal systems, including noise effects, will be investigated. The design, which will be a stand-alone die with digital circuits operating at subthreshold power supply voltages and integral on-die regulation, will include radiation hardened by design approaches. The low voltage (and variable voltage) operation will allow simulation and measurement of the hardening efficacy vs. voltage using the final fabricated die. This will also allow determination of irradiation effects for very low voltage operation.

 

 

Radiation-Tolerant SiGe BiCMOS Smart MMICs for Space Communications

University-Industry Team: Deuk Heo (WSU) with Fong Shi (Boeing)

In this AFRL project, we will investigate and implement radiation-tolerant SiGe BiCMOS smart MMICs for upper X-band or lower Ku band LEO satellite phase array communication systems. SiGe RF circuit blocks such as SPDT T/R switches, phase shifters, attenuators based on PIN diodes, high IIP3 SiGe LNAs and SiGe power amplifiers will be developed using advanced topology to improve the overall power added efficiency and linearity. In addition to the investigation of cost-effective microstrip and coplanar RF interconnect methodologies, the project will include the development of radiation-tolerant mixed signal RF circuits with low power digital implementations taking advantage of the BiCMOS technology. Special design and layout methodologies will be developed to improve the SiGe circuit performance for radiation tolerant communication applications. We are planning to use IBM SiGe 5HP/AM BiCMOS process or better process to implement the circuit blocks. Based on initial simulation, we will finalize the technology node for the circuit implementation. The developed circuit blocks can be smoothly migrated to the IBM SiGe 7HP BiCMOS process, when the fabrication cost is affordable.

The proposed project is in synch with AFRL research focus areas of radiation-tolerant standard cells with mixed signal RF circuits including passive elements for space communications, reconfigurable RF transmitters and receivers using novel silicon-based PIN diode SPDT components and system-on-a-chip implementation. This research will be performed in partnership with Boeing. We will perform pre-radiation test of RF subsystems and SiGe devices which are available in WSU and develop radiation tolerant SiGe smart MMICs for space

communications based on the measurement and characterization results. The radiation tolerance of developed passives and RF SiGe subsystems will be verified with TID test up to 200 krad.

 

 

Direct Digital Frequency Synthesizer for Reconfigurable Communication Systems 

University-Industry Team: George La Rue (WSU) with Fong Shi (Boeing)

        This project continues the investigation of direct digital frequency synthesizers (DDFSs) in silicon-on-insulator (SOI) CMOS technology for space applications. DDFSs provide very fast frequency hopping, low phase noise and high frequency resolution, which are important requirements for many modern wireless communication systems. DDFSs are more versatile than VCO based synthesizers and are reconfigurable after deployment to meet a wide variety of applications. This is important for space applications where the life of a mission can be very long, requirements may change and replacing electronics after deployment is usually not an option.    

        The research focuses on the investigation of nonlinear DAC approaches for the implementation of DDFSs to reduce power dissipation and complexity. A 12-bit DDFS using a 32-segment piecewise-linear approximation to the sinusoid and the lookup table was implemented using Honeywell’s radiation-tolerant MOI5 0.35 µm SOI CMOS process. The pipelined phase accumulator limits operation of the DDFS in simulations to about 1.4 GHz and contributes the majority of the power dissipation of 1.6W. The printed circuit board test fixture and device packaging are nearly completed and testing will begin within next two weeks.

        We are also modeling and will soon be measuring radiation effects on FETs with various radiation-hardened layouts using TSMC’s 0.18 micron CMOS process. We will use these devices to implement a radiation-hardened quadrature output DDFS with 14-bit resolution operating at 2 GSps. The higher resolution should increase the SFDR by about 10 dB to near 80 dB. A piecewise-quadratic approximation will be used to further reduce the ROM look-up table. A parallel phase accumulator architecture will be used to reduce power dissipation and SEU detection and correction of the critical logic and registers will be included. Total power dissipation should be reduced to less than 200 mW. 

 

SOI CMOS Continuous-Time Delta Sigma A/D Converters for Space Communication Radio Receivers 

University-Industry Team:  Adrian Leuciuc and Alex Doboli (SUNY) with Bruce Ohme (Honeywell)

Radiation hardening by design techniques are investigated, both at the system and circuit levels, for a specific class of mixed-signal systems: oversampling delta-sigma A/D converters. We are using a bottom-up approach for obtaining behavioral single-effect radiation models for all analog cells used in continuous-time DS modulators implemented in SOI CMOS technology. Behavioral simulations at the system-level characterize the effects of single event hits and maximal values for the duration and amplitude of the single-event transients are obtained for each building block in the system. The analog cells are then designed to meet the requirements of both radiation-free specifications and to achieve the desired radiation immunity.

 

 Radiation-Hard PLL Design Tolerant to Noise and Process Variations

University-Industry Team: Un-Ku Moon and Karti Mayaram (OSU) with Andy Peczalski (Honeywell)

This project addresses the design of radiation hard and noise tolerant phase-locked loops

(PLLs) for frequencies greater than 1GHz in the Honeywell 0.35µm SOI CMOS (MOI-5) process. The overall focus is on a systematic design methodology for radiation-hard, noise tolerant PLLs in SOI CMOS processes. New circuits and architectures will be developed and combined with self- calibration methods and radiation hardened layout techniques. The self-calibration methods will enable tuning out process, temperature, threshold voltage, and supply voltage variations yielding a robust design. Floating-body devices will be compared with body-tied devices in the context of the PLL design and their effect on the PLL jitter/phase noise performance will also be evaluated.

 

RF, Analog and Digital Array for Radiation-Hardened Communication Circuits

University-Industry Team: Larry McMurchie and Carl Sechen (UW) with Andy Peczalski (Honeywell)

This research will accomplish two goals. The first goal is a better understanding of the effects of radiation, particularly Single Event Effects (SEUs), primarily in digital circuits. While the effects of radiation on RAM cells has been thoroughly studied and numerous remediation techniques proposed, Single Event Transients (SETs) have not been widely studied. Few remediation techniques other than TMR-in-hardware have been proposed. We believe that a variety of techniques, particularly TMR-in-time and register filtering, can achieve the same radiation hardness, without incurring a 3X area/throughput/power hit.

As a demonstration vehicle, we chose a coarse-grained reconfigurable analog/digital architecture. We believe that such a reconfigurable architecture has a large power/speed/area/functionality advantage over existing fine-grained commercial FPGAs. In terms of radiation hardness, the reconfigurability of the architecture allows an additional benefit: the degree of radiation hardness can be a programmable feature.

In addition to our work with SETs and SEUs, we have developed a set of total-dose-hardened cells. These cells are based upon a bulk CMOS process and employ edgeless devices. The cells are parametrizable, so that a range of sizes can be generated. 

 

Radiation Hardening by Design for Data Converters

University-Industry Team:  Gabor Temes (OSU) with Andy Peczalski (Honeywell)

        The main goal of this work is the development of novel architectures, circuitry and design methodologies for radiation-hardened, high-speed and high linearity, current-steering digital-to-analog (DACs) interfaces realized in conventional CMOS technology. The key target of the project is the design and implementation of a radiation-insensitive delta-sigma digital modulator, using digital correction to enhance linearity and to correct for radiation and mismatch effects. It will also utilize a novel unit-element current matrix for the reduction of total-dose-effects (TDE). Sigma Delta converters are not strongly affected by single-event-effects (SEE), since they operate on the principle of storing and averaging many input signal samples to obtain each output sample. The linearity correction developed by us has similar properties. The effects of radiation have been addressed also at the circuit level, and investigated based on device physics considerations. Specialized circuitry with low sensitivity to radiation is being developed. Finally, the dimensions and layout of the devices will be established so as to minimize radiation effects and to maximize the yield. The critical components that are subject to single-events-upset (SEU) in the modulator, in the correction circuitry, and in the digital interpolation filters associated with the design have been identified. These will be designed with special care, and (if necessary) will incorporate redundant elements.

The devices will be designed for fabrication in a well characterized and inexpensive commercial CMOS technology (such as a 4M-2P 0.35μm one), and will be tested at OSU for electrical performance. We also plan to perform laser testing for single-event effects using the University of Oregon's picosecond laser facility, as soon as testable chips are available.