A CMOS Alamouti Diversity Transmitter
David Allstot and Sumit Roy (University of Washington)

Investigation of Design and Post-Process Trimming of a Sub-1 V Bandgap in Deep Sub-Micron CMOS Technology
Benjamin Blalock (University of Tennessee)

Adaptive Regulation and Logic for Subthreshold Circuits
Lawrence Clark (Arizona State University)

Advanced Input Pad Design for RF CMOS
R. Bruce Darling (University of Washington)

High Frequency Delta-Sigma ADCs
Terri Fiez (Oregon State University)

Low-Voltage High Speed Mixed-Signal Circuits for Wired and Wireless Transceivers
Deuk Heo (Washington State University)

SiGe Data Converter Circuits

George La Rue (Washington State University)

Low-Voltage Analog Circuits in CMOS
Un-Ku Moon (Oregon State University)

Design of High-Accuracy and Robust Data Converters
Thing Nguyen and Gabor Temes (Oregon State University)

High-Performance Sample-and-Hold Amplifiers
Gabor Temes (Oregon State University)

On-Chip Interconnect Models for High-Frequency/Speed Integrated Circuits on Silicon Substrate
Andreas Weisshaar (Oregon State University) 

CDADIC Funded Projects, 2005-2006

 A CMOS Alamouti Diversity Transmitter

Principal Investigator: David Allstot and Sumit Roy (University of Washington)

Participating Student: Subhanshu Gupta and Nathan Neihart 

Investigation of Design and Post-Process Trimming of a Sub-1 V Bandgap in Deep Sub-Micron CMOS Technology 

Principal Investigator: Benjamin Blalock (University of Tennessee)

Participating Student: Suheng Chen

The primary objective of this work is to research the post-process trimming methodology of the sub-1 V bandgap voltage reference (BGR) and investigate the circuit issues such as stability, line regulation, and lower supply operation, in order to gain in-depth understanding and to facilitate its adoption in commercial applications. As semiconductor processes scale down to 130 nm and lower, the recently developed sub-1 V BGR circuit topology is replacing the conventional BGR since its approximate output voltage of 1.25 V is higher than the process-specified supply. In addition, sub-1 V BGR literature has not yet reported on the important issue of sub-1 V BGR post-process trimming. If conventional post-process trimming techniques are applied to the sub-1 V BGR, significant error and potentially additional cost can result. This research will investigate post-process trimming of the sub-1 V BGR to achieve an efficient approach for commercial applications. Also, sub-1 V BGR circuit issues will be further investigated, including stability and start-up issues that are unique to the sub-1 V architecture, as well as line regulation.

Benefits to Industry Partners: This work will research the sub-1 V BGR post-process trimming methodology, which can be applied to the manufacturing process and potentially drive down the post-process cost of the sub-1 V BGR. The investigation and improvement of circuit issues will also be applicable to a wide range of low voltage analog design in very deep sub-micron CMOS.

 

 

Adaptive Regulation and Logic for Subthreshold Circuits

Principal Investigator: Lawrence Clark (Arizona State University)

Participating Student: Ted Chen and Jinhui Chen

Low power system on chip (SoC) designs are increasingly important to diverse applications ranging from hand-held cell phones and PDAs, medical devices such as pacemakers, to military applications including wearable computing and communications, and space systems. Most of the IC’s aimed at such applications must cope with limited battery capacity and thermal capability. Present commercial system on chip (SOC) designs have dozens of supply voltage domains for power savings, SRAM stability, and independent power down capabilities. Based on present trends, even more independent supplies can be expected in the future. This allows lower power, but invites the difficult problem of generating the supply voltages either at the board or die level.

This research pertains to the development of both RHBD (and non-hardened) CMOS circuit techniques to allow very low operating voltage, i.e., both in and/or near subthreshold operation with on-die voltage down conversion and high efficiency regulation. Integration with large mixed signal systems, including noise effects, will be investigated. The design, which will be a stand-alone die with digital circuits operating at subthreshold power supply voltages and integral on-die regulation, will include radiation hardened by design approaches. The low voltage (and variable voltage) operation will allow simulation and measurement of the hardening efficacy vs. voltage using the final fabricated die. This will also allow determination of radiation effects on very low voltage operation.

Benefits to Industry Partners: Minimizing power is critical for lightweight battery powered systems. Commercial industrial applications include wearable, hand-held, and cellular communications IC’s, and circuits that must operate while an SOC is in standby. Military applications include ultra-low power modes for space applications, wearable and portable electronic systems.

Advanced Input Pad Design for RF CMOS

Principal Investigator:  R. Bruce Darling (University of Washingtoin)

Participating Student:  Tom Christiansen

The objective of this research program is to develop improved pad frame designs which can better complement and support the advancing state-of-the-art in analog, mixed-signal, and RF CMOS integrated circuits.  Modern high frequency integrated circuits place conflicting requirements on analog I/O pads to provide both high fidelity signal transmission and buffering along with sufficient protection against electrostatic discharge (ESD) and electrical overstress (EOS) transients.  The series bondwire inductances and pad-to-package and pin-to-package shunt capacitances already limit the I/O bandwidth of these interconnects, while any ESD protection devices contribute additional shunt parasitic capacitance and reduce the bandwidth further.  In order to provide a certain level of ESD protection, the ESD protection devices must have sufficient size to absorb the energy from the transient, but devices with larger size introduce proportionally more parasitic capacitance.  

The proposed research will develop new pad frame circuits, new ESD protection device layouts, and new signal multiplexing and buffering techniques to produce better optimized trade-offs between ESD/EOS protection levels, signal bandwidth and fidelity, pin count, and package parasitic elements.  These same techniques will also be useful in developing IC pad frame circuits and interfacing techniques which can be applied to more demanding environmental conditions and more aggressive levels of system-on-a-chip (SoC) integration.  An important part of this research program is the development of advanced characterization and testing methods for analog signal integrity through the pad frame.  This involves high speed transient testing using novel pulse generators and on-chip diagnostic circuitry in the time domain, as well as more traditional network and impedance analysis in the frequency domain. 

Benefits to Industry Partners:  This work will develop some new RF CMOS IC input pad designs and some new ESD protection device layouts which may be useful to the sponsoring companies.  Several companies have expressed interest in developing and testing these designs in collaboration with us. 

High Frequency Delta-Sigma ADCs - Efficient Far Field RF Energy Harvesting

for Passively Powered Sensors

Principal Investigator:  Terri Fiez (Oregon State University)

Participating Students:  Zhimin Li, Triet Le, and Yuhan Xie

The performance bottleneck of most mixed-signal systems is the A/D converter. As

process dimensions reduce to realize the cost-performance benefits predicted by Moore’s

Law, it becomes more difficult to obtain both high speed and high-resolution A/D

converters required in many modern communication systems. The focus of this project is

to complete the testing and characterization of a new high speed and high resolution

ADCs and demonstrate its performance through fabrication and measurement. This will

be complete in the first three months. Then the focus will be on developing an extension

to this architecture. While this background work is in progress, we will develop new far

field RF-energy harvesting techniques that can be used with passive devices. This is

particularly useful when battery replacement is not feasible for various sensing

applications. 

Benefits to Industry Partners:  The techniques being developed in this project are applicable to other mixed-signal circuits. Additionally, other novel circuit techniques are expected to be developed through this design.

Low-Voltage High Speed Mixed-Signal Circuits for Wired and Wireless Transceivers

Principal Investigator:  Deuk Heo (Washington State University)

Participating Students:  Parag Upadhyaya and Yang Zhang

Advancements in multi-gigahertz wired and wireless communication technology catering to high data rate requirements prompt the investigation of innovative low cost, low power and low voltage high-speed mixed signal circuits. In both wired and wireless communication the communication bandwidth is heavily dependent on the quality of the signal source or the frequency synthesizer which includes voltage controlled oscillator (VCO). The phase noise of the VCO determines the quality of the carrier as the phase noise is a measure of signal spread. For multi-channel application, if the signal spreads from one channel to adjacent channels, it would increase the noise level and thus reduce the signal to noise ratio (SNR) of that particular channel as well as limiting data bandwidth. In wired communication the phase noise translates into rms jitter of the clock which degrades transceiver performance in jitter generation, jitter tolerance and jitter transfer which will lead to increased bit error rate (BER). So to improve the quality of both wire and wireless communication we intend to investigate novel methods and techniques for improving phase noise of the VCO.

In the ensuing research period, our research will have two major thrusts: (i) Development of low voltage and low jitter PLL based on low phase noise VCO operating at 5 GHz to be used for both 5 GHz ISM Band RF transceivers and 10 Gbps (OC198) wired transceivers, and (ii) Investigation of a wide tuning range (4.8GHz to 6.3 GHz) or multi-band low phase noise LC VCO for a PLL to cover 10 Gbps wired transceivers, 3.125 Gbps (XAUI) wired transceivers, and 2.4 GHz and 5 GHz wireless ISM band transceivers covering IEEE 802.11a/b/g.

Benefits to Industry Partners:  Low voltage and low power VCO with low phase noise will help mitigate performance degradation that in many cases is the bottleneck for DCR and image reject receivers. Additionally a low phase noise VCO translates into low rms jitter in the wired communication which helps wired transceiver meet jitter tolerance and jitter generation and improves the BER rates. This research will greatly benefit member companies in transceiver applications as well as companies interested in clock generation and PLLs.

SiGe Data Converter Circuits 

Principal Investigator: George La Rue (Washington State University)

Participating Students: Dirk Robinson

This project will continue to investigate high-speed data converter circuits in SiGe BiCMOS technology. The focus of the research will be to increase accuracy of analog-to-digital converters (ADCs) with conversion rates in the 250 MSps to 4 GSps range.  These ADCs have applications in high-bandwidth communications and instrumentation.  Compared to flash converters, multi-stage converters have far fewer components and with the addition of pipelining the throughput approaches that of flash converters.  Another approach to achieve high speed is to interleave a number of slower speed ADCs.  A key component in both pipelined multi-stage and interleaved architectures is an accurate track-and-hold amplifier (THA) circuit.  THAs relax the timing requirements for subsequent quantizers but non-ideal behavior causes distortion of the analog input signal, many times limiting performance of the ADC. The goals of this project are to demonstrate THAs with 12-bit accuracy at 1 GSps and up to 14 bits at 300 MSps.  We designed, laid out and fabricated two THAs using different architectures and various compensation techniques with simulated accuracy of 11-bits at 1 GSps, which is a bit short of the goal.  We will investigate several approaches to improve the THA accuracy in the coming year.  We will also investigate ADC architectures and implementations to achieve low-power and high accuracy ADCs to go along with the THAs.  We will investigate methods to use low-cost CMOS trimming circuits to compensate for errors due to process mismatches and non-ideal components in the predominately bipolar ADC building blocks for increased accuracy.  We will characterize the ADC building blocks we designed this year and combine these into a 12-bit ADC at 1 GSps during the next year.

Benefits to Industry Partners:  Many member companies use ADC circuits in their products or provide ADC products. This work will help to increase understanding of the effect different approaches and compensation techniques have on the performance of high-speed high-accuracy THAs and ADCs in SiGe technology. THAs are key to building high-performance high-linearity ADCs. An advantage of using SiGe BiCMOS technology for ADCs over other high-speed technologies, such as InP and GaAs HBT, is the availability of low-power CMOS with high-integration levels.  This opens up freedom to provide extensive calibration and error correction on-chip to improve accuracy without significant degradation in yield or increase in power dissipation. Increased accuracy of high-speed ADCs will result from methods and techniques developed in this work.

Low-Voltage Analog Circuits in CMOS

Principal Investigator: Un-Ku Moon (Oregon State University)

Participating Students:  P. Kurahashi, G. Ahn, and Y. Kook

       This research focuses on developing new circuit techniques suitable for current and future low-voltage submicron CMOS processes. Various IC solutions have been targeted over the years in the area of switched-capacitor circuits, data converters, and filters. Current research focus is in the area of highly linear and tunable low-voltage continuous-time filters. This research is unique in that it entirely avoids the use of voltage boosting or bootstrapping techniques. This allows all techniques developed under this research to be fully compatible with submicron CMOS processes. Our past work in the low-voltage topic has produced new low-voltage switched-capacitor techniques utilizing active opamp reset method, which can overcome the inherent speed limitations of the well known switched-opamp technique. We also developed new tuning scheme for low-voltage filters which effectively compensates for the master-slave mismatches by incorporating both direct (foreground on power-up) and indirect (background) tuning techniques. Our current research thrust in Switched-R-MOSFET-C (SRMC) architecture has shown promising results for truly low-voltage and highly linear filter design. While it has long been accepted that the low voltage and high linearity are two contradictory and unachievable combination of design goals, our SRMC architecture is about to counter that traditional view.

Benefits to Industry Partners:  Industry member companies will benefit from our research progress and results in low-voltage circuits (e.g. opamp-reset, switched-RMOSFET-C) that overcome inherent low-voltage limitations. These techniques may be adopted by industry member companies for future state-of-the-art, low-voltage CMOS processes. Our low voltage research efforts will also summarize an important and practical set of analog circuit design considerations for current and future submicron CMOS processes.

Design of High-Accuracy and Robust Data Converters 

Principal Investigator: Thing Nguyen and Gábor Temes (Oregon State University)

Participating Students: Jose Luis Ceballos, Zhenyong Zhang

The purpose of this project is (a) to continue research on the High-Performance Delta-Sigma Modulators (DSMs)) and (b) to develop new architectures for robust delta-sigma converters based on stochastic approach. For the DSM project, we have developed a novel dual-path multi-bit DSM for the efficient DAC error correction using a correlation-based algorithm [1]. To verify this new structure, a prototype test chip with over-sampling ratio (OSR) of 4 and sampling rate of 8 Mbps is being designed. For the robust DSM project, we propose the use of spatial redundancy topology, in which a set of M one-bit comparators, operating in parallel and dithered by a large zero-mean random signal, is used to obtain a multi-bit quantized output signal. Preliminary simulation results confirmed the theoretical prediction, and verified that the intrinsic memory of the system helps to maintain the assumed statistical properties. Futhermore, the proposed architecture is more robust than the conventional DSM due to the following: (a) The operations of the proposed circuit will continue to function at a slightly reduced SNR in case a sufficiently small number of 1-bit comparators cease to function and (b) there is no need for accurate reference voltages, hence the requirements for DAC accuracy may be relaxed.

Benefits to Industry Partners: The continuing project on dual-path delta-sigma ADCs is aimed at extending the frequency range and/or accuracy of ADCs used in communications, digital video, radar systems, and other commercially important fields. This will be useful for companies active in one or more of these areas. The new project on data converters using multiple coarse quantizers will have applications in sensor networks, and also in converters operating in hazardous environments where robustness is of importance, such as radiation-exposed ADCs and DACs, or converters subject to high temperature, as is the case in automotive electronics. They promise robust performance, and more gradual deterioration under destructive conditions.

High-Performance Sample-and-Hold Amplifiers

Principal Investigator: Gábor Temes (Oregon State University)

Participating Students: To be determined

Sample-and-hold (S/H) and track-and-hold (T/H) amplifiers are among the key components of fast and/or high-resolution analog-to-digital converters (ADCs). They are used in pipeline ADCs, as well as in successive-approximation, counting and two-step ADCs. They are also used in high-accuracy flash ADCs. S/H circuits need to acquire accurately the samples of a time-varying waveform, and transform them into a piecewise-constant signal for the following stages. It is important to make this operation robust with respect to the nonidealities of the circuit components, especially those of the amplifier used in the S/H stage.

In the proposed research, we shall develop improved S/H structures for low-voltage/low-power applications in high-speed and/or high-accuracy systems. These stages should operate preferably by passive functions (e.g.,charge-sharing), and rely minimally on the properties of the amplifiers used. They should be widely applicable in a variety of data converters. We shall select a suitably challenging application (such as a fast high-accuracy pipeline ADC) to validate the new concepts and circuits.

Benefits to Industry Partners: Sample-and-hold amplifiers are key components in most state-of-art data converters. Having access to novel SHAs, which are more accurate, more linear, and/or faster than existing ones, should be beneficial to companies that design and fabricate data converters as part of their product lines.

On-Chip Interconnect Models for High Frequency/Speed Integrated Circuits on Silicon Substrate

Principal Investigator: Andreas Weisshaar (Oregon State University)

Participating Students: Chris Blevins, Joel Kolstad, Erik Vernon, and Mike Montague

The main objective of this project is to develop algorithms and implement tools for automated CADmodel generation from S-parameter data for general 3-D interconnects and passive structures. The generated CAD models are compatible with commercial circuit simulators and design tools. During this year we have developed the “Circuit Augmentation Method” (CAM), which combines traditional equivalent circuit modeling with the latest mathematical “macro-modeling” techniques. CAM thereby starts with the information and physical intuition of a hand-crafted circuit model and takes advantage of the inherent accuracy and speed of the generation of an abstract “black box” or “macromodel.” This new approach is aimed at significantly reducing engineering time spent on model development. During this year we have developed a basic model generation tool for two-, three-, and four-port (i.e. two coupled) interconnect structures. The main anticipated innovations for the coming year include: (i) extension of CAM to multiport 3-D interconnect structures (multiple coupled interconnects); (iii) pre-determination of augmentation topology; (ii) a library of basic equivalent circuit models for common interconnect topologies; (iv) inclusion of fabrication tolerances; (v) implementation of tool in commercial design environments.

Benefits to Industry Partners: This modeling methodology is being developed in collaboration with Tektronix. The novelty of this approach is in combining the physical insight of equivalent circuit modeling with the flexibility and automation of black-box modeling. The main benefit of this project to industry is the availability of a general modeling methodology and tool to automate development and extraction of compact models from S-parameter data for a wide range of high frequency passive structures and components. This project is of high relevance to CDADIC companies involved with high-frequency and high-speed circuit design. The algorithms and tools for automated generation of CAD models for interconnects and passive components are expected to help to significantly reduce engineering time for model development and improve circuit design accuracy.