Twisted Inductors with Low Coupling for Mixed-Signal/RF ICs
David Allstot (University of Washington)

A 6-bit, 10GS/s, 50mW DAC Transmitter and a 5-bit, 10GS/s, 50mW ADC Receiver for High-Speed Serial Links
Patrick Yin Chiang (Oregon State University)

On-Chip Temperature Sensors for Deep Submicron CMOS
R. Bruce Darling (University of Washington)

Investigation of a Fully Integrated Frequency Based Current to Digital Converter
Ethan Farquhar and Ben Blalock (University of Tennessee)

High Frequency Delta-Sigma ADCs for Low Power Communication Systems

Terri Fiez (Oregon State University)

Low-Voltage High Speed Mixed-Signal Circuits for Wired and Wireless Transceivers
Deuk Heo (Washington State University)

Low-Voltage Analog Circuits in CMOS
Un-Ku Moon (Oregon State University)

Low-Power, Low Jitter/Phase-Noise BAW-Based PLL 
Brian Otis (University of Washington)

Low-Power Delta-SIgma A/D Converters 
Gabor Temes (Oregon State University)

Coupling Suppression in Integrated Circuits Using Dummy Metal Fill 
Andreas Weisshaar (Oregon State University)

Ultra-Low Power, Parallel Serial Link Interfaces Using Resonant Clocking and
Digitally Calibrated Phase/Gain Process Compensation
Patrick Yin Chiang (Oregon State University)

Advanced Gate Models for Deep Submicron CMOS Circuit Simulation
R. Bruce Darling (University of Washington)

Low-Power All-Digital Chip-to-Chip Interface Circuits

Pavan Kumar Hanumolu (Oregon State University)

Nanoscale Clock and Date Recovery Circuits
George La Rue (Washington State University)

Coupled Devices and Circuit Simulation for Analyzing the Effect of Random Dopant and Geometry Fluctuations in Analog/RF Integrated Circuits
Karti Mayaram (Oregon State University)

Stochastic and Passive A/D Techniques for Submicron CMOS
Un-Ku Moon (Oregon State University)

Reconfigurable Master/Slave Locked Low Noise Amplifiers 
Brian Otis (University of Washington)

Highly Configurable and Robust Data Converters 
Gabor Temes (Oregon State University)

CDADIC Funded Projects, 2007-2008

 Twisted Inductors with Low Coupling for Mixed Signal/RF ICs

Principal Investigator: David Allstot (University of Washington)

Participating Student: Nathan Neihart and Parmoon Seddighrad

A 6-bit, 10GS/s, 50mW DAC Transmitter and a 5-bit, 10GS/s, 50mW ADC Receiver for High Speed Serial Links

Principal Investigator: Patrick Chiang (Oregon State University)

Participating Student: Jing-Guang Wang

Conventional 10Gb/s serial links for chip-to-chip communication use high speed, analog/mixed-signal circuits with complex analog equalizing filters and clock/data-recovery circuits.  Such circuits are difficult to port to future deep submicron technology and become less effective at higher data rates in lossy channels (i.e. 20Gb/s). Instead, we propose designing an entire digital transmitter/receiver system for 10Gb/s serial links using a programmable 6-bit DAC and 5-bit ADC in 65nm CMOS, burning approximately 100mW (analog).  This all-digital conversion architecture will then allow for digital timing recovery, digital equalization schemes, (i.e. DFE, partial response), where the digital power dissipation reduces exponentially with continued transistor scaling.  While a similar transceiver has been built before in 2001 for serial link applications, the power consumed in this 0.25um CMOS technology is 15x more than our proposed implementation in 65nm CMOS.  We are proposing a transceiver dissipating 200mW(100mW digital) for each 10Gb/s serial link channel, such that the power consumption will approach the power of conventional, mixed-signal, complex, equalized transceivers. (i.e. IBM’s 10Gb/s DFE/FFE transceiver burns 300mW. Benefits to Industry Partners: The area of high-speed (> 1GHz), low-resolution (4-6 bit) ADC converters are useful for many applications, including ultra wideband receiver front-ends, optical receivers, and multi-gigahertz serial links. The application of high-speed DACs/ADCs to serial links has been recently proposed by Texas Instruments. Other companies (i.e. Intel) have researched building such Flash A/D converters, but the power is still exceedingly high. By applying the techniques of resonant clocking to significantly reduce power consumption, we can begin considering practical 10Gb/s transceivers using DACs/ADCs, allowing for future more complex modulation schemes (i.e. duobinary, 4-PAM, 8-PAM) and digital timing recovery schemes.

 

On-Chip Temperature Sensors for Deep Submicron CMOS

Principal Investigator: R. Bruce Darling (University of Washington)

Participating Student: TBA

Compact, high-accuracy, wide-range temperature sensors will be developed for use in deep-submicron CMOS processes where high power densities require on-chip temperature sensing for proper power management. The desired performance specifications include a measurement range of 0°C to 125°C with a worst case error of ±1°C, minimum trimming for proper two-point calibration, and a simple and compact digital interface to the host digital system into which the circuit would be embedded. The design will also strive to minimize power dissipation and die area, so that the circuit has low implementation overhead. Two types of proportional-to-absolute-temperature (PTAT) circuits will be developed.  The first will use MOSFETs operated deep into their subthreshold characteristics to provide the needed exponential current-voltage characteristic. The second will use low-current well diodes which also exhibit an exponential current-voltage characteristic.  Both of these approaches will be designed to produce a PTAT output current at a level of a few mA, significantly lower than presently reported designs. The output PTAT current will be used in a current-controlled oscillator which will function as a temperature-to-frequency (T/f) converter. The output square wave will then clock a simple N-bit ripple counter, whose output count is also proportional to absolute temperature.  This allows for a completely software-controlled calibration, since the gating period of the counter sets the gain, and the offset or preload value sets the °F or °C offset point. This approach does not require a voltage-based ADC or a voltage reference.  Benefits to Industry Partners: These temperature sensor circuits should provide a new, low-overhead alternative to conventional bipolar PTAT circuits, and provide a compact means for on-die temperature sensing as part of power management systems. Possible applications would include DRAMs, video processors, DSP engines, CPUs, wireless transceivers, and other subsystems which operate at high power densities. 

 

Investigation of a Fully Integrated Frequency Based Current to Digital Converter

Principal Investigator:  Ethan Farquhar and Ben Blalock (University of Tennessee)

Participating Students:  Xiaoyan Yu

The quest for ultra low power systems is requiring lower and lower current levels in circuits.  Frequently these currents need to be precisely measured, but off chip solutions tend to be slow, costly, and noisy.  The aim of this work is to develop a novel frequency based current to digital converter which can be completely realized on an integrated circuit, reducing the noise and cost, while increasing the speed at which readings can be made.  Modifications to this system will also allow for a single system which can convert both analog voltages and currents to digital codes.  Accuracy should be related to relative capacitor sizes, and array size.  The range of the system is tunable to accommodate many different current ranges, and can be designed such that it watches many different ranges simultaneously. Benefits to Industry Partners:  It is believed that industry members will see an immediate benefit in applications which require precise bias currents to be present.  The system provides for simple on chip measurement of very low currents, and with a few modifications could also provide for a single system which could convert both currents and voltages to a digital representation all on the same chip.  It has the benefit of working best with subthreshold currents which makes it particularly suited for lower power applications.  

 

High Frequency Delta-Sigma ADCs for Low Power Communication Systems

Principal Investigator:  Terri Fiez (Oregon State University)

Participating Students:  Yuhan Xie

The performance bottleneck of most mixed-signal systems is the A/D converter.  As process dimensions reduce to realize the cost-performance benefits predicted by Moore’s Law, it becomes more difficult to obtain both high speed and high-resolution A/D converters required in many modern communication systems.  Designing Δ-Σ A/D converters with MHz signal bandwidths and more than 14-bit dynamic range is a challenging topic for both industry and academia.  Additionally, with the need for portable communication electronics, it is imperative that the data converter operate with very low power.   This past year, we have developed a new architecture for continuous-time Δ-Σ A/D converter that is a generalized approach applicable for 14-bit, 20 MHz and power dissipation targeted at 20mW as shown in Fig. 1.  Low power is achieved through the novel architecture that has very low component spread, thus reducing the drive circuit power requirements (op amp).  Coupled with the architecture is an implementation that uses only 3 op amps for a 5th order architecture, Fig. 2.  This reduces the DC operating power significantly. Benefits to Industry Partners:  The techniques we are developing are applicable to other mixed-signal circuits.  Additionally, we expect other novel circuit techniques will be developed as we work through the design.

 

Low-Voltage High Speed Mixed-Signal Circuits for Wired and Wireless Transceivers

Principal Investigator:  Deuk Heo (Washington State University)

Participating Students:  Parag Upadhyaya, Pinping Sun, and Liu Peng

While significant research has already been poured into signal generation and phase noise improvement, the constant desire for further improvement and higher data bandwidth demands more rigorous and novel improvements to help foster such a growth. In both wired and wireless communication, the data bandwidth is heavily dependent upon the quality of the signal source or the frequency synthesizer; however, PLLs come with their own unique set of challenges. They inherently take a long time to lock, require very low noise VCO in potentially noisy environments, consume significant power, need large silicon area and force trade-offs between key performance parameters. This problem puts wireless applications in an unenviable position, as they are driven by low power, low cost, and high performance operation. Low-power constraints demand that PLLs be turned off during inactivity, but then require that they lock quickly when turned back on. Therefore, the investigation of low cost, low power, and high quality novel fast locking PLLs is driven by the tight demand of state-of-the art wideband applications.  Our objectives for the forthcoming research period will address aforementioned challenges with two parallel thrusts: (i) investigation of IPs for low voltage and low jitter inductor-less PLL, and (ii) low voltage and low jitter PLL based on novel LC VCOs, a low spur and low glitch charge pump, and a low power divider design. These works will result in innovative PLL for applications covering OC192, XAUI and PCI-Express wired transceivers and wireless transceivers meeting IEEE 802.11a/b/g, WiMAX (IEEE802.16) standards.

Benefits to Industry Partners:  Low voltage and low power VCO and QVCO with low phase noise and low phase error, respectively, will help mitigate performance degradation that in many cases are the bottleneck for DCR and image-reject receivers. Additionally, a low phase noise VCO translates into low RMS jitter in wired communications, which helps the wired transceiver meet jitter tolerance and jitter generation and improves the BER rates. The low power IPs, including low power VCO, tunable active inductor , very low power analog frequency dividers, and fast-locking PLL concepts, will greatly benefit member companies in transceiver application as well as companies who are interested in clock generation and PLLs.

Low-Voltage Analog Circuits in CMOS

Principal Investigator: Un-Ku Moon (Oregon State University)

Participating Students:  Peter Kurahashi

Our past work in the low-voltage topic has produced new low-voltage switched-capacitor techniques utilizing active opamp reset method, which can overcome the inherent speed limitations of the well known switched-opamp technique. We also developed new tuning scheme for low-voltage filters which effectively compensates for the master-slave mismatches by incorporating both direct (foreground on power-up) and indirect (background) tuning techniques. The Switched-R-MOSFET-C (SRMC) architecture has shown excellent results for truly low-voltage and highly linear filter design. While it has long been accepted that the low voltage and high linearity are two contradictory and unachievable combination of design goals, our SRMC architecture counters this traditional view.  Our latest research into low-voltage tunable mixers shows a novel way to tune the bandwidth of passive style mixers while operating at low voltages.  As a continuation of our low-voltage work, we propose the adaptation of the linear duty-cycle based tuning to an IF-to-baseband quadrature ∆Σ ADC structure. As digital processes become faster, analog-to-digital data converters are able to process higher frequency signals. The trend in wireless receivers is to move the data conversion closer to the antenna to reduce complexity and lower cost of receiver systems. IF-to-Baseband ∆Σ modulators have been shown to be effective in digitizing IF. For these architectures to be applicable to future processes, they must operate at low voltages and be robust to process variation.  To provide proper noise-shaping, noise transfer function zeros must be set accurately. These constrains necessitate the use of low-voltage tuning in continuous-time ∆Σ structures.Benefits to Industry Partners:  Our industry member companies are to benefit from our research progress and results in low-voltage circuits (e.g. opamp-reset, switched-R-MOSFET-C) that overcome inherent low-voltage limitations. These techniques may be adopted by the industry member companies for future state-of-the-art low-voltage CMOS processes. Our low voltage research efforts will also summarize an important and practical set of analog circuit design considerations for current and future submicron CMOS processes

Low-Power, Low Jitter/Phase-Noise BAW-Based PLL

Principal Investigator: Brian Otis (University of Washington)

Participating Students: Shailesh Rai  and Julie Hu 

This project will comprise an investigation of two topics: 1.) We will analyze, design, and fabricate an inductor-free, low power, low phase-noise/jitter frequency synthesizer and 2.) We will investigate quadrature oscillator I/Q phase error calibration architectures. Both of these tasks will directly build on the results from our FY2007 CDADIC project, where we demonstrated the use of matched high Q bulk-acoustic wave (BAW) resonators as a method of improving the tradeoff between oscillator power consumption and phase-noise and reduce wasted die area in a 2GHz QVCO [1][2]. Digital RF transceiver architectures increasingly require quadrature (I/Q) local oscillator sinusoid generation to allow highly-integrated image-reject or direct-conversion architectures. In this project, we will tackle two important topics that will enable a new generation of low power frequency synthesizers: a phase-locked BAW VCO and a quadrature VCO phase calibration scheme.  Benefits to Industry Partners: Task 1 benefits: In our previous CDADIC work, we introduced the power/noise benefits of emerging resonator technologies. In this work, we will demonstrate their practical use by developing new PLL topologies with very low power consumption and jitter/phase noise. This analysis will help member companies assess future passive component technologies as well as emerging frequency synthesizer architectures. Task 2 benefits: This task will result in a new quadrature VCO frequency generation calibration scheme that is immediately applicable to member companies. The calibration loop can be continuously run in the background and consumes very little power/area. This technique is general to all VCO topologies. 

 

Low-Power Delta-Sigma A/D Converters

Principal Investigator: Gábor Temes (Oregon State University)

Participating Students: Jeong Seok Chae, Weilun Shen and Yan Wang

One of the key problems of mixed-mode electronics is the development of high-accuracy analog-to-digital converters, with low power dissipation. Such converters have applications in consumer electronics, radar systems, and other important areas. The inherent accuracy and simplicity of delta-sigma ADCs make them a natural choice for such a task. However, when the required signal bandwidth is very wide, combined with high resolution (over 12 bits) and low power dissipation (less than 10 milliwatts), delta-sigma converter design becomes challenging. Two different approaches have been proposed, using discrete-time circuitry (using switched-capacitor filters) or continuous-time circuitry (using Gm-C or RC filters and current-source D/A converters). Under the proposed research, we shall explore both of these alternatives, using some new approaches. Benefits to Industry Partners: The proposed research will allow the design of low-power and accurate ADCs, useful in consumer electronics (e.g., cell phones, digital video) and other applications.

 

Coupling Suppression in Integrated Circuits Using Dummy Metal Fill 

Principal Investigator: Andreas Weisshaar (Oregon State University)

Participating Students: Vikas Shilimkar

We propose to utilize dummy metal fill in integrated circuits to reduce coupling and crosstalk noise between critical circuit components. Our approach is in contrast to the currently used techniques that aim at mitigating the parasitic effects of fill cells.  Our proposed approach is expected to lead to improved isolation between components and interconnects thus reducing spacing requirements and enabling denser circuit layouts.  We plan to develop a comprehensive set of models and new design approaches for coupling and crosstalk suppression using grounded and floating metal-fill cells. We will demonstrate the effectiveness of the proposed approach on representative example cases and technologies. The new metal-fill strategy is proposed to be fully automated and incorporated into the standard circuit design and layout phases.  Benefits to Industry Partners:  Availability of a general design methodology and designs for interconnects and inductors using metal-fill cells for coupling and crosstalk suppression.   Help improve the design and performance of ICs fabricated in advanced processes.   CDADIC industry members will become more aware of the impact and importance of metal-fill patterning in modern IC design and fabrication technologies using CMP.

Ultra-Low Power, Parallel Serial Link Interfaces Using Resonant Clocking and Digitally Calibrated Phase/Gain Process Compensation

Principal Investigator: Patrick Chiang (Oregon State University)

Participating Student: TBD

Future CMOS processes (65nm and below) will contain an enormous amount of transistors for system-on-a-chip possibilities (Figure 0).  For example, future SOCs may contain hundreds of heterogeneous parts (ALUs, GPUs,  MIMO baseband processors,  embedded memory) which are communicating on-chip with each other, or off-chip with components like memories other processors. While the ability to perform a huge amount of computation will be theoretically possible, what becomes one of the most significant bottlenecks will be in “feeding” such computation units with data. Thus, the design of high speed serial link interconnects (on and off die) are a critical component to nanoscale microelectronics. With this research plan, we will attempt to improve by more than an order of magnitude three central issues in on/off-chip parallel digital interfaces: power consumption, aggregate data bandwidth, and immunity/robustness to significant process variation.  Benefits to Industry Partners:  The design of low-power parallel serial links, both on and off chip, are a significant problem for future nanoscale system-on-a-chip designs.  Recent discussions and meetings with Intel, IBM, and others suggest that large bandwidth, low-power, parallel interfaces tolerant of process variation are a critical component for achieving peak, realizable utilization of hundreds of disconnected, computational units.

 

 

Advanced Gate Models for Deep Submicron CMOS Circuit Simulation

Principal Investigator: R. Bruce Darling (University of Washington)

Participating Student: Eric K. Black

Scaling of CMOS is now dominated by gate engineering techniques which include high-k gate dielectrics (e.g., HfO₂, HfN, HfSiO_x) and new gate metal materials (e.g., TiN, TaN). These new materials and gate stacks introduce effects which are not observed in conventional SiO₂ gate MOSFETs, and which are not accurately represented in the present generation of circuit simulation models.  Gate leakage currents are a primary concern with further device scaling, and with high-k gate dielectric stacks, new leakage mechanisms such as Fowler-Nordheim tunneling, Frenkel-Poole emission, and threshold voltage instabilities have been related to interfacial defect states. These physical mechanisms cause significant departure from the conventional models of gate conduction and capacitance. The proposed research will address the need for accurate gate models to support circuit design in this new generation of CMOS gate technology. The proposed research plans to develop a gate leakage current model from calculations of the tunneling currents due to direct tunneling, Fowler-Nordheim tunneling, Shockley-Read-Hall defect state recombination, and Frenkel-Poole defect state emission. This model will be coded as a 4-terminal SPICE device model which can be added in parallel to an existing MOSFET to more accurately represent the gate current components.  After the model has been developed, it will be used to simulate a selection of benchmark circuits, both digital, analog, and mixed-signal, in several of the more promising high-k gate dielectric process technologies. This modeling work will help to simulate the performance effects of porting an existing circuit design in a conventional SiO₂ gate process to a high-k gate dielectric process. It will also provide a means for predicting the impact of a gate stack modification on down-stream circuit performance, and for selecting the most appropriate CMOS gate technology for a particular application. 

Benefits to Industry Partners: High-k gate dielectric processes, some with metal gates, are becoming the standard for deep submicron CMOS in the 45nm and smaller nodes.  Providing accurate device models for these new technologies will benefit circuit designers who must make informed tradeoffs between circuit performance and process technology. 

 

Low-Power All-Digital Chip-to-Chip Interface Circuits

Principal Investigator: Pavan Kumar Hanumolu (Oregon State University)

Participating Students: Brian Young, Bangda Yang, Jon Guerber, and Brian Dros

This project addresses the design of scalable low-power chip-to-chip links in deep submicron digital processes. The emphasis is on the implementation of analog functions using either all-digital or pseudo-digital circuits. In particular, a new low-power continuous-time equalizer that uses a digital adaptation loop and an all-digital phase locked loop, and all-digital clock and data recovery circuits are proposed. Self calibration techniques to suppress the effect of process variations are investigated. Built-in-self test methods that reconfigure the existing circuits to measure important link performance metrics such as voltage margins, jitter tolerance are explored.

Benefits to Industry Partners:  The proposed digitally intensive calibration schemes will enable implementing precision analog functions in processes that experience very large parameter variations. In particular, the proposed design techniques will enable all-digital links with better than 5mW/Gbps power efficiencies.

 

High Frequency Delta-Sigma ADCs for Low Power Communication Systems

Principal Investigator:  Terri Fiez (Oregon State University)

Participating Students:  Yuhan Xie

The performance bottleneck of most mixed-signal systems is the A/D converter.  As process dimensions reduce to realize the cost-performance benefits predicted by Moore’s Law, it becomes more difficult to obtain both high speed and high-resolution A/D converters required in many modern communication systems.  Designing Δ-Σ A/D converters with MHz signal bandwidths and more than 14-bit dynamic range is a challenging topic for both industry and academia.  Additionally, with the need for portable communication electronics, it is imperative that the data converter operate with very low power.   This past year, we have developed a new architecture for continuous-time Δ-Σ A/D converter that is a generalized approach applicable for 14-bit, 20 MHz and power dissipation targeted at 20mW as shown in Fig. 1.  Low power is achieved through the novel architecture that has very low component spread, thus reducing the drive circuit power requirements (op amp).  Coupled with the architecture is an implementation that uses only 3 op amps for a 5th order architecture, Fig. 2.  This reduces the DC operating power significantly. Benefits to Industry Partners:  The techniques we are developing are applicable to other mixed-signal circuits.  Additionally, we expect other novel circuit techniques will be developed as we work through the design.

 

Nanoscale Clock and Data Recovery CIrcuits

Principal Investigator:  George La Rue (Washington State University)

Participating Students:  Bill Hamon

Many applications require clock and data recovery (CDR) circuits for high-speed data communication. This project researches clock and data recovery circuits (CDRs) in STMicroelectronics’ 65 nm technology to have high tolerance to device and process variations, extremely wide tuning range, very low jitter, low power and require only a small amount of layout area. The robustness to process variations, small area and low supply voltages is a result of minimizing the analog functions to calibrated digital-controlled delays. A novel digital-controlled clock synthesizer (DCS) replaces the voltage controlled oscillator (VCO) in the phase-locked loop (PLL) of the CDR to enable instantaneous frequency hopping and operation at all data rates below a maximum frequency above 10 GHz. The CDR is reconfigurable to operate over many protocols and data rates. The CDR will be designed with hardness-by-design techniques and with sufficient margin to handle the wide process variations and a large temperature range. Because no analog filter is required in the PLL, die area is reduced substantially. Benefits to Industry Partners: Digital microprocessors, FPGAs and ASICs contain many PLLs and DLLs to handle clock skew and high-speed I/O. The DCS provides much smaller area than PLLs. DLLs are also mostly digital but the DCS is capable of synthesizing frequencies with low jitter. Many applications in communications can benefit from the versatility of this DCS and CDR because of the extremely large tuning range, low jitter, small size and fast frequency hopping.

 

Coupled Device and Circuit Simulation for Analyzing the Effect of Random Dopant and Geometry Fluctuations in Analog/RF Integrated Circuits

Principal Investigator:  Karti Mayaram (Oregon State University)

Participating Students: TBD

A coupled device/circuit simulator will be enhanced to include coupled device and circuit level sensitivity analysis for determining the impact of random fluctuations on the performance of analog/RF circuits. Since the device simulator models (numerical models) are predictive, they can be used to evaluate the impact of technology on circuit performance. Coupled device/circuit simulation will be essential for the analysis of random fluctuations in analog/RF ICs fabricated in nanoscale process technologies.

Benefits to Industry Partners: Parameter variability is an important concern for nanoscale devices. AFRL and commercial sector will benefit by having a simulator that will accurately predict the effect of these variations on the performance of analog/RF circuits in nanoscale technologies. This will enable robust design in the presence of variability.

 

Stochastic and Passive A/D Techniques for Submicron CMOS

Principal Investigator: Un-Ku Moon (Oregon State University)

Participating Students:  Ben Hershberg and Skyler Weaver

Stochastic and passive conversion techniques are proposed as high performance and low power analog to digital data converter architectures. Using knowledge of the random nature of device mismatch it is possible to employ stochastic techniques, allowing the use of many smaller and less accurate components to save power and area while maintaining accuracy. Additional benefits include high scalability and high yield/robustness with process variation, voltage, temperature, and radiation. A complementary and parallel research objective of this proposal is to investigate passive analog-to-digital conversion techniques, specifically passive SAR and delta-sigma A/D converters. While there are a variety of possibilities for passive techniques to be applied to a wide range of applications, there is a particularly promising potential for this to be applied in the context of a stochastic converter. Implementing a stochastic converter as a back-end ADC will open the door to new types of hybrid architectures to be investigated, particularly with the intent of advancing the state-of-the-art in low power A/D converters. Benefits to Industry Partners: The redundancy of a stochastic A/D architecture can be exploited to increase product yield and product life. Mobile and distributed applications can benefit from the reduced power requirements of stochastic A/Ds and passive conversion techniques.

 

Reconfigurable Master/SLave Locked Low Noise Amplifiers

Principal Investigator: Brian Otis (University of Washington)

Participating Students: Steve Zafonte and Will Biederman

The next generation of military and commercial wireless systems must accommodate two increasingly important factors: the need for extreme reconfigurability and the requirement of low power dissipation. This reconfigurability is driven by the following: the ability to cope with large process variations/design uncertainty, the need to operate across multiple wireless standards, and operation in various SNR/interference scenarios. In this project, we will develop a frequency locked LNA that can accommodate process/design uncertainty as well as allow operation over a wide range of LNA bias points. This allows dynamic variation of the LNA bias current, allowing a power consumption savings over a static worst-case operating point.  As the process nodes shrink, the inductors do not. Consequently the amplifier remains nearly the same size while the real cost multiplies. This leads to increasing cost of fabricating and/or feature stagnation at a particular price point. The ability to reuse the same amplifier for multiple bands would significantly alleviate this. By the end of the project, we will have performed a detailed analysis of frequency locked LNAs and have fabricated a prototype test-chip to validate our analysis. Benefits to Industry Partners: Industry is currently facing a crisis with the area consumed by on-chip inductors. This problem is exacerbated by the following trends: the push towards smaller feature sizes and the need for multi-band single-chip transceivers. These same problems are faced in the military sector, especially with the need to have ubiquitous communication devices that span a broad range of military/civilian wireless standards. Our technique is general enough to be used by many types of transceiver architectures, so it should find universal application in many commercial and military sectors.

 

Highly Configurable and Robust Data Converters

Principal Investigator: Gábor Temes (Oregon State University)

Participating Students: Kyehyung Lee, Jeongseok Chae, and Rishi Gupta

We shall develop programmable delta-sigma ADCs, with the resolution, bandwidth and power dissipation externally controlled by a digital input word. The structure contains a number of interconnected unit-cell ADCs, which are internally coupled for improved performance, and which can be powered up or down to achieve a controlled trade-off between their performance and power dissipation. The proposed research is tailored to AFRL Research Area 3. It will result in data converters that are reconfigurable to meet a variety of standards, can be realized with low-gain amplifiers, and are tolerant of element imperfections, including those caused by radiation or extreme temperatures. Benefits to Industry Partners: Since nanoscale fabrication is now widely used in industry, the circuit design techniques developed under this project will be applicable in commercial projects as well as AFRL ones