CDADIC - Projects, 2005-2006

Investigation of a High-Performance, Pipelined ADC Operating with a Very Low Supply Voltage
Benjamin J. Blalock (University of Tennessee)
Abstract – This proposal describes a new effort for the design and implementation of a 10-bit, 10-MSps
pipelined ADC which operates with a supply voltage of 0.5-V. It will be targeted for the 90-nm CMOS
process node. Many issues are associated with analog design at such a low supply voltage; the most
significant issue is the design of high-performance operational amplifiers. Therefore, most of the initial
effort in this project will be to create an op amp which meets the requirements for use in the pipelined ADC. The group at UT is well prepared to meet the challenges of this design having experience in low-voltage analog design, design of high gain-bandwidth product op amps, and design of pipelined ADCs.
Design Techniques Enabling 10+ GSs, 6b, < 100mW ADCs - Patrick Chiang (Oregon State University)
Abstract - The design of analog/mixed-signal equalization (i.e. TX/RX FIRs, RX-DFEs) for serial links speeds greater than 10Gbps is extremely difficult, as the optimal equalization coefficients and signal processing algorithm may vary widely for different channels. For next generation serial links in the 10+ Gbps data rate, an alternative architectural partition is to implement an analog-to-digital converter with the equalization performed entirely in the digital domain [TI, ISSCC2007].This architecture allows for a flexible equalization algorithm to be implemented for a large range of very lossy channels. 10+ GSs, low-resolution ADCs are also important for future mm-wave RF transceivers, since the ADC must downconvert several gigahertz of baseband bandwidth. However, the design of a 10+ GSs, 6b [5 ENOB], ADC in deep submicron CMOS is extremely difficult, in regards to power consumption, timing jitter, and power supply noise rejection. The goal of this research is to understand the fundamental limitations to the design of 10+ GSs, 6b, analog-to-digital converters in deep submicron CMOS. The critical requirements are: power dissipation; power supply noise rejection; minimal jitter generation. For a 12.5GSs, 6b [5 ENOB], < 100mW ADC, the design can be partitioned into two parts: 1) Low-power (< 20mW), 1.5GHz, multi-phase (8-phase) clock generation, calibration, and distribution 2) Low-power (< 10mW), 1.5GHz, 6b [5 ENOB] sub-ADC We currently have designed a calibration algorithm that achieves < 1ps residual phase offset. This technique uses phase binning to determine the phase spacing between adjacent phases. In addition, we introduce a technique called “statistical averaging”, where the inherent offset of the measurement circuits are averaged out. We also have developed some new techniques for power-supply rejection, by building the on-die regulator with a on-die bypass in parallel with a large, offchip bypass capacitance, giving -30dB PSRR across a frequency range from 1MHz-1GHz. Finally, we have been exploring the use of low-power, self-timed quantizers in conjunction with a charge-sharing successive-approximation 1.5GHz, 6b ADC. By implementing 2b/stage, the number of quantizer conversions < 10, with preliminary simulations exhibiting < 10mW for the entire sub-ADC.

On-Chip Temperature Sensors for Deep Submicron CMOS - Robert Bruce Darling (University of Washington)
Abstract - Compact, high-accuracy, wide-range temperature sensors are being developed for use in deepsubmicron CMOS processes where high power densities require on-chip temperature sensing for proper power management. The desired performance specifications include a minimum measurement range of 0°C to 125°C with a worst case error of ±1°C, minimum trimming for proper two-point calibration, and a simple and compact digital interface to the host digital system into which the circuit would be embedded. The designs also strive to minimize power dissipation and die area, so that the complete temperature measurement system has low implementation overhead. Both the temperature sensors themselves and the analog-to-digital converters which would work with them are being considered simultaneously within the scope of this work as an integrated solution. These designs differ from existing temperature measurement systems by having a very fast response time of 20 μs (50 kS/s), so that fast thermal loading and unloading events can be managed by this type of sensor system. Two fundamentally different approaches to temperature sensing are currently under investigation, a subthreshold MOSFET proportional-to-absolute-temperature (PTAT) circuit, and direct temperaturecontrolled oscillator (TCO) circuits. The first uses the exponential current-voltage characteristics of a subthreshold MOSFET, while the second uses the nearly linear temperature dependence of the MOSFET threshold voltage. New work is proposed to examine if the temperature dependence of the MOSFET gate leakage can be used as an effective temperature sensor. Data converters for the outputs of these temperature sensors are also being developed, and several architectures are under investigation, including ΣΔ converters and frequency counter architectures. New work is proposed to further develop a technique called time-ratioed sensing and conversion (TRSC), which, similar to dual-slope and incremental ΣΔ converters, allows cancellation of many of the elements which would normally require independent calibration.


Ultra Low-power, Low-jitter Frequency Synthesizers Using Digital Multiplying Delay-Locked Loops and Charge Recycling - Pavan Kumar Hanumolu (Oregon State University)
Abstract - The goal of our proposed research is to explore and invent system- and circuit-level design techniques that will enable ultra low-power clock generators. Particular emphasis is on the implementation of digital multiplying delay-locked loops that offer the following benefits: (a) ultra low-power realization due to the absence of power-hungry voltage controlled oscillator present in a conventional phase-locked loop and (b) reduced deterministic jitter due to the use of digital circuitry as opposed to mismatch-sensitive analog circuits. Further, charge-recycling techniques that exploit un-scaled supply voltages in deep sub-micron CMOS processes to lower power dissipation will be investigated.

Highly Linear Body-Enabled High Speed Analog and Multi-band RF Circuits - Deuk Heo (Washington State University)
Abstract - Multi-standard and multi-band operations greatly increase technical requirements and place a large strain on the linearity and harmonic suppression requirements of high speed analog and RF circuits. The conventional techniques applied to improve linearity, dynamic range and reduce receiver noise figure in sub-micron technologies do not adequately meet performance requirements. Triple-well FETs with a deep N-well, now common in most scaled CMOS processes, can be exploited to advance circuit performance. The signal on the body terminal (DC and AC) can be configured to reduce threshold voltage, increase transconductance, reduce phase noise and lower the noise figure via innovative body enabled techniques such as body biasing, body coupling, body floating and body bias calibration for mismatch compensation. However, there has not been enough research to address possible challenges and benefits of body enabled high speed analog and RF circuits. The objective of this proposal is to investigate body enabled linearity enhancement techniques and the low voltage analog and multi-band RF front-end architectures with maximum hardware sharing based on a scaled CMOS technology. These techniques can be applied to low noise amplifiers, RF switches, mixers, single or multi-phase voltage controlled oscillators, variable gain amplifiers, and power amplifiers to improve their respective performance; during this first year, we will focus on the investigation of a highly linear multi-band LNA and low phase noise LC VCOs and conduct initial exploratory study of a silicon based RF switch which incorporates body enabled methods. The outcome of this work includes innovative IPs and design methodologies for wireline and wireless communication applications.

Single-Ended 16 x 10 Gbps Data Bus - George La Rue (Washington State University)
Abstract - As CMOS technology continues to scale with higher speed, density and integration levels, input/output (I/O) capacity becomes even more of a bottleneck. With the advent of multi-core processors, I/O bandwidth needs to scale not only with the higher speed of the technology but by an additional factor of the number of cores. Current data rates of a few Gbps are standard and rates are expected to increase soon to 10 Gbps. At these high data rates, the natural inclination is to use differential signaling because of its insensitivity to noise. However, two pins are required per I/O and PCB routing area doubles. If the same data rates can be achieved with single-ended signaling, the I/O capacity can nearly double for the same number of I/O pins. We will investigate methods to resolve three issues to allow single-ended signaling to achieve data rates nearly equal to that of differential signaling: reducing power supply bounce, reducing crosstalk and compensating for lack of common mode rejection. Single-ended I/Os are not necessarily balanced, which increases power supply bounce that not only affects signals on the single-ended bus but can affect other signals on the transmitting chip. Coding across groups of lines
will be used to equalize the number of high and low levels. Codes that minimize pin count and power dissipation will be determined. We will explore compensation methods to reduce crosstalk from adjacent signals in the group both at the transmitter and receiver. To provide the equivalent of common mode rejection for differential pairs, the common mode voltage of a group of signals will be determined and the thresholds of each comparator in the group will be adjusted accordingly. To show the effectiveness of these techniques for high-speed low-power single-ended I/O, we will design a 16-channel transceiver chip in 90 nm technology and demonstrate a 16-bit bus with a throughput of over 160 Gbps over 5 to 10 inches of FR-4 material with about 20 I/O pins. We will also include test structures to compare performance to differential I/Os.

Low-Voltage Analog Circuits in CMOS – Un-Ku Moon (Oregon State University)
Abstract - Our past work in the low-voltage topic has produced new low-voltage switched-capacitor techniques utilizing active opamp reset method, which can overcome the inherent speed limitations of the well known switched-opamp technique. We also developed new tuning scheme for low-voltage filters which effectively compensates for the master-slave mismatches by incorporating both direct (foreground on power-up) and indirect (background) tuning techniques. The Switched-R-MOSFET-C (SRMC)
architecture has shown excellent results for truly low-voltage and highly linear filter design. Our most
recent research into low-voltage tunable mixers shows a novel way to tune the bandwidth of passive style
mixers while operating at low voltages. As a continuation of our low-voltage work, we propose the adaptation of the linear duty-cycle based tuning to a quadrature ΔΣ ADC structure. Zero/pole tuning in continuous time ΔΣ modulators is often achieved through binary weighted element arrays. This method of tuning adds parasitic capacitance to the signal path, lowering the maximum bandwidth of these systems. For a large tuning range and high resolution, this method also uses a large portion of die area. Complications can arise when tuning for process, voltage, and temperature (PVT) variations with an element array. Because the tuning is discrete in nature, signal corruption can occur during switching while adjusting for voltage and temperature. By applying the SRMC architecture to a continuous-time ΔΣ modulator, a highly tunable system can be constructed with limited disruption to the signal path. This system will also carry with it the advantages of the SRMC architecture which include high linearity, low voltage operation and the ability to continuously tune for PVT variations.


Wideband Low-Power Continuing Proposal Delta-Sigma A/D Converters - Gabor Temes (Oregon State University)
Abstract - High-accuracy wide-band analog-to-digital converters with low power dissipation are key components used in communication systems, consumer electronics, radar systems and in medical applications. The target of the proposed project is to develop delta-sigma ADCs with signal bandwidths of 25 MHz or more, combined with high resolution (over 12 bits) and low power dissipation (less than 20 mW). These devices, and the design techniques developed for them, will be useful for next-generation wireless and video systems. We shall explore both discrete-time and continuous-time architectures to achieve these goals.

A Low Power, Low Jitter Fractional-N Frequency Synthesizer with Wide-tuning BAW-stabilized VCO - Brian Otis (University of Washington)
Abstract - We propose to tackle an increasingly important problem: accurate and efficient inductor-free RF frequency references for low noise clocking and local oscillator signal generation. This issue has become especially critical in portable systems where low power consumption is demanded but performance cannot be sacrificed. Increased data bandwidth and system integration demand low power and high performance RF oscillators that are compatible with the mainstream CMOS processes. To date, we have shown extremely promising results using miniaturized RF MEMS resonators to create novel RF oscillators and synthesizers. This year, we will address the drawback that we frequently hear from our industrial mentors: overcoming the limited tuning range of high Q MEMS-based oscillators.

Coupling Suppression in Integrated Circuits using Dummy Metal Fill - Andreas Weisshaar (Oregon State University)
Abstract - This project aims at characterizing the performance degradation of RF components due to dummy metal fill required in advanced IC processes and improving electrical isolation between circuit components in RF/mixed-signal ICs via strategic patterning and grounding of the dummy metal fill. Our new design approach using metal fill leads to improved performance or smaller chip size, especially when spacing is isolation/ crosstalk driven. We have developed new design strategies for in-plane metal fill giving improved isolation with minimum loading tradeoff. We have also studied and quantified the effect of finite grounding impedance, high frequency effects, and the impact of metal fill on MIM capacitors. For our future work we plan to develop fast extraction methods for metal fill parasitics, compact device
models incorporating metal fill, as well as optimized slotting strategies for metal traces. Furthermore, we
plan to characterize and model the degradation of inductor performance (Q and self-resonant frequency)
and transmission line characteristics (characteristic impedance and phase velocity) due to metal fill. We
plan to fabricate and test representative RF structures to validate our characterization and modeling
approaches and design strategies.